VLSI (4361102) - Summer 2024 Solution

Question 1(a) [3 marks]

Draw the structure of FinFET and write its advantages.

Answer:

Table: FinFET Advantages

Mnemonic: "BCR - Better Control Reduces leakage"

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Question 1(b) [4 marks]

Explain depletion and inversion of MOS structure under external bias

Answer:

Table: MOS Bias Conditions

Diagram:

goat

• Depletion: Positive gate voltage creates electric field pushing holes away
• Inversion: Higher voltage attracts electrons forming conducting channel

Mnemonic: "DI - Depletion Inverts to conducting channel"

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Question 1(c) [7 marks]

Explain n-channel MOSFET with the help of its Current-Voltage characteristics.

Answer:

Table: MOSFET Operating Regions

Key Equations:

• Linear: ID = μnCox(W/L)[(VGS-VTH)VDS - VDS²/2]

• Saturation: ID = (μnCox/2)(W/L)(VGS-VTH)²

• Structure: Gate controls channel between source and drain

• Operation: Gate voltage modulates channel conductivity

• Applications: Digital switching and analog amplification

Mnemonic: "CLS - Cut-off, Linear, Saturation regions"

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Question 1(c OR) [7 marks]

Define scaling. Compare full voltage scaling with constant voltage scaling. Write the disadvantages of scaling.

Answer:

Definition: Scaling reduces device dimensions to increase density and performance.

Table: Scaling Comparison

Disadvantages:

• Short Channel Effects: Channel length modulation increases
• Hot Carrier Effects: High electric fields damage devices
• Quantum Effects: Tunneling currents increase significantly

Mnemonic: "SHQ - Short channel, Hot carriers, Quantum effects"

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Question 2(a) [3 marks]

Draw two input NAND gate using CMOS.

Answer:

goat

Table: NAND Truth Table

Mnemonic: "PP-SS: Parallel PMOS, Series NMOS"

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Question 2(b) [4 marks]

Explain noise immunity and noise margin for nMOS inverter.

Answer:

Table: Noise Parameters

• VIL: Maximum low input voltage
• VIH: Minimum high input voltage
• Good noise immunity: Large noise margins prevent false switching

Mnemonic: "HILOL - High/Low Input/Output Levels"

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Question 2(c) [7 marks]

Explain Voltage Transfer Characteristics (VTC) of CMOS inverter.

Answer:

Table: VTC Regions

Key Features:

• Sharp transition: Ideal switching behavior
• High gain: Large slope in transition region
• Rail-to-rail: Output swings full supply range

Mnemonic: "ASH - A-region, Sharp transition, High gain"

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Question 2(a OR) [3 marks]

Implement NOR2 gate using depletion load nMOS.

Answer:

goat

Table: NOR2 Truth Table

Mnemonic: "DPN - Depletion load, Parallel NMOS"

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Question 2(b OR) [4 marks]

Differentiate between enhancement load inverter and Depletion load inverter.

Answer:

Table: Load Inverter Comparison

• Enhancement: Requires positive gate voltage for conduction
• Depletion: Conducts with zero gate voltage
• Performance: Depletion load provides better characteristics

Mnemonic: "EPDLH - Enhancement Positive, Depletion Lower power, Higher speed"

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Question 2(c OR) [7 marks]

Explain Depletion load nMOS inverter with its VTC.

Answer:

Circuit Operation:

• Load transistor: Always conducting (VGS = 0, VT < 0)
• Driver transistor: Controlled by input voltage
• Output: Determined by voltage divider action

Table: Operating Points

VTC Characteristics:

• VOH: VDD (better than enhancement load)
• VOL: Lower due to depletion load characteristics
• Transition: Sharp switching between states

Mnemonic: "DLB - Depletion Load gives Better high output"

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Question 3(a) [3 marks]

Implement EX-OR using Depletion load nMOS.

Answer:

goat

Table: XOR Truth Table

Implementation: Y = A⊕B = A'B + AB'

Mnemonic: "XOR - eXclusive OR, different inputs give 1"

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Question 3(b) [4 marks]

Explain design hierarchy with example.

Answer:

Table: Hierarchy Levels

Benefits:

• Modularity: Independent design and testing
• Reusability: Common blocks used multiple times
• Maintainability: Easy debugging and modification

Mnemonic: "SMG-T: System, Module, Gate, Transistor levels"

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Question 3(c) [7 marks]

Draw and explain Y chart design flow.

Answer:

Table: Y-Chart Domains

Design Flow:

• Top-down: Behavioral → Structural → Physical
• Bottom-up: Physical constraints influence upper levels
• Iterative: Multiple passes for optimization

Mnemonic: "BSP - Behavioral, Structural, Physical domains"

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Question 3(a OR) [3 marks]

Implement NAND2 - SR latch using CMOS

Answer:

goat

Table: SR Latch Operation

Mnemonic: "SR-HRI: Set, Reset, Hold, Invalid states"

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Question 3(b OR) [4 marks]

Which method is used to transfer pattern or mask on the silicon wafer? Explain it with neat diagrams

Answer:

Method: Lithography - Pattern transfer using light exposure

Process Steps:

Applications: Creating gates, interconnects, contact holes

Mnemonic: "CED - Coating, Exposure, Development"

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Question 3(c OR) [7 marks]

Which are the methods used to deposit metal in MOSFET fabrication? Explain deposition in detail with proper diagram.

Answer:

Table: Metal Deposition Methods

Sputtering Process:

• Ion bombardment: Argon ions hit target material
• Atom ejection: Target atoms knocked off
• Deposition: Atoms settle on wafer surface
• Control: Pressure and power determine rate

Advantages:

• Uniform thickness: Excellent step coverage
• Low temperature: Preserves device integrity
• Variety: Multiple materials possible

Mnemonic: "IBE-DC: Ion Bombardment Ejects atoms for Deposition Control"

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Question 4(a) [3 marks]

Implement Z= ((A+B+C)·(D+E+F). G)' with depletion nMOS load.

Answer:

goat

Logic Implementation:

• First level: (A+B+C) and (D+E+F) OR functions
• Second level: AND with G
• Output: Inverted result due to nMOS structure

Mnemonic: "POI - Parallel OR, Inversion at output"

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Question 4(b) [4 marks]

List and explain the design styles used in VERILOG.

Answer:

Table: Verilog Design Styles

Characteristics:

• Behavioral: Describes what circuit does
• Structural: Shows how components connect
• Mixed: Combines multiple styles for complex designs

Mnemonic: "BDSG - Behavioral, Dataflow, Structural, Gate-level"

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Question 4(c) [7 marks]

Implement NAND2 SR latch using CMOS and also implement NOR2 SR latch using CMOS.

Answer:

NAND2 SR Latch:

verilog

NOR2 SR Latch:

verilog

Table: Latch Comparison

Key Differences:

• NAND: Set/Reset with low inputs
• NOR: Set/Reset with high inputs
• Feedback: Cross-coupled gates maintain state

Mnemonic: "NAND-Low, NOR-High active"

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Question 4(a OR) [3 marks]

Implement Y= (ABC + DE + F)' with depletion nMOS load.

Answer:

goat

Implementation Logic:

• ABC: Series connection (AND function)
• DE: Series connection (AND function)
• F: Single transistor
• Result: Y = (ABC + DE + F)' due to inversion

Mnemonic: "SSS-I: Series-Series-Single with Inversion"

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Question 4(b OR) [4 marks]

Write Verilog Code to implement full adder.

Answer:

verilog

Table: Full Adder Truth Table

Logic Functions:

• Sum: Triple XOR operation
• Carry: Majority function of inputs

Mnemonic: "XOR-Sum, Majority-Carry"

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Question 4(c OR) [7 marks]

Implement Y =(S1'S0'I0 + S1'S0 I1 + S1 S0' I2 + S1 S2 I3) using depletion load

Answer:

Note: Assuming S2 in last term should be S0.

verilog

Table: Multiplexer Selection

Circuit Implementation:

• Decoder: S1, S0 generate select signals
• AND gates: Each input ANDed with corresponding select
• OR gate: Combines all AND outputs

Mnemonic: "DAO - Decoder, AND gates, OR combination"

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Question 5(a) [3 marks]

Implement the logic function G = (PQR +U(S+T))' using CMOS

Answer:

goat

Implementation:

• pMOS: Parallel for OR, Series for AND (inverted logic)
• nMOS: Series for AND, Parallel for OR (normal logic)
• Result: De Morgan's law applied automatically

Mnemonic: "PSSP - Parallel Series Series Parallel"

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Question 5(b) [4 marks]

Implement 8×1 multiplexer using Verilog

Answer:

verilog

Table: 8:1 MUX Selection

Mnemonic: "Case-Always: Use case statement in always block"

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Question 5(c) [7 marks]

Implement 4 bit full adder using structural modeling style in Verilog.

Answer:

verilog

Structural Features:

• Module instantiation: Four 1-bit full adders
• Carry chain: Connects carries between stages
• Hierarchical design: Reuses basic full adder module

Table: Ripple Carry Addition

Mnemonic: "RCC - Ripple Carry Chain connection"

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Question 5(a OR) [3 marks]

Implement logic function Y = ((AF(D + E) )+ (B+ C))' using CMOS.

Answer:

goat

Logic Breakdown:

• Inner term: AF(D + E) = A AND F AND (D OR E)
• Outer term: (B + C) = B OR C
• Final: Y = (AF(D + E) + (B + C))'

CMOS Implementation:

• PMOS network: Implements complement of function
• NMOS network: Implements original function
• Result: Natural inversion provides Y

Mnemonic: "PNAI - PMOS Network Applies Inversion"

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Question 5(b OR) [4 marks]

Implement 4 bit up counter using Verilog

Answer:

verilog

Table: Counter Sequence

Features:

• Synchronous reset: Reset on clock edge
• Auto rollover: 1111 → 0000
• 4-bit range: Counts 0 to 15

Mnemonic: "SRA - Synchronous Reset with Auto rollover"

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Question 5(c OR) [7 marks]

Implement 3:8 decoder using behavioral modeling style in Verilog.

Answer:

verilog

Table: 3:8 Decoder Truth Table

Key Features:

• Behavioral modeling: Uses always block and case statement
• Enable control: All outputs disabled when enable = 0
• One-hot output: Only one output active at a time
• 3-bit input: Selects one of 8 outputs

Applications:

• Memory addressing: Chip select generation
• Data routing: Channel selection
• Control logic: State machine outputs

Mnemonic: "BEOH - Behavioral Enable One-Hot decoder"