VLSI Technology (4353206) - Summer 2025 Solution

Question 1(a) [3 marks]

Draw neat labeled diagram of physical structure of n-channel MOSFET.

Answer:

Diagram:

goat

Key Components:

• Source: n+ doped region providing electrons
• Drain: n+ doped region collecting electrons
• Gate: Metal electrode controlling channel
• Oxide: SiO2 insulating layer
• Substrate: p-type silicon body

Mnemonic: "SOGD - Source, Oxide, Gate, Drain"

Question 1(b) [4 marks]

Draw energy band diagram of depletion and inversion of MOS under external bias with MOS biasing diagram. Explain inversion region in detail.

Answer:

MOS Biasing Circuit:

goat

Energy Band Diagrams:

Inversion Region Details:

• Strong inversion: VG > VT (threshold voltage)
• Electron channel: Forms at Si-SiO2 interface
• Channel conductivity: Increases with gate voltage
• Threshold condition: Surface potential = 2φF

Mnemonic: "DIVE - Depletion, Inversion, Voltage, Electrons"

Question 1(c) [7 marks]

Explain I-V characteristics of MOSFET.

Answer:

I-V Characteristic Regions:

Characteristic Curve:

goat

Key Parameters:

• μn: Electron mobility
• Cox: Gate oxide capacitance
• W/L: Width to length ratio
• VT: Threshold voltage

Operating Modes:

• Enhancement: Channel forms with positive VGS
• Square law: Saturation region follows quadratic relationship

Mnemonic: "CLS - Cutoff, Linear, Saturation"

Question 1(c) OR [7 marks]

Define scaling. Explain the need of scaling. List and explain the negative effects of scaling.

Answer:

Definition: Scaling is the systematic reduction of MOSFET dimensions to improve performance and density.

Need for Scaling:

Scaling Types:

Negative Effects:

• Short channel effects: Threshold voltage roll-off
• Hot carrier effects: Device degradation
• Gate leakage: Increased tunneling current
• Process variations: Manufacturing challenges
• Power density: Heat dissipation issues

Mnemonic: "SHGPP - Short channel, Hot carrier, Gate leakage, Process, Power"

Question 2(a) [3 marks]

Implement Y' = (AB' + A'B) using CMOS.

Answer:

Logic Analysis: Y' = (AB' + A'B) = A ⊕ B (XOR function)

CMOS Implementation:

goat

Truth Table:

Mnemonic: "XOR needs complementary switching"

Question 2(b) [4 marks]

Explain enhancement load inverter with its circuit diagrams.

Answer:

Circuit Diagram:

goat

Configuration:

Operation:

• Load transistor: Acts as active load resistor
• High output: Limited by VT of load transistor
• Low output: Depends on driver strength
• Disadvantage: Poor VOH due to threshold drop

Transfer Characteristics:

• VOH: VDD - VT (degraded high level)
• VOL: Close to ground potential
• Noise margin: Reduced due to threshold loss

Mnemonic: "ELI - Enhancement Load Inverter has threshold Issues"

Question 2(c) [7 marks]

Explain Voltage Transfer Characteristic of inverter.

Answer:

VTC Parameters:

VTC Curve:

goat

Noise Margins:

• NMH = VOH - VIH (High noise margin)
• NML = VIL - VOL (Low noise margin)

Regions:

• Region 1: Input low, output high
• Region 2: Transition region
• Region 3: Input high, output low

Quality Metrics:

• Sharp transition: Better noise immunity
• Symmetric switching: VM = VDD/2
• Full swing: VOH = VDD, VOL = 0

Mnemonic: "VTC shows VOICE - VOH, VOL, Input thresholds, Characteristics, Everything"

Question 2(a) OR [3 marks]

Explain NAND2 gate using CMOS.

Answer:

CMOS NAND2 Circuit:

goat

Truth Table:

Operation:

• PMOS network: Parallel connection (pull-up)
• NMOS network: Series connection (pull-down)
• Output low: Only when both inputs high

Mnemonic: "NAND - Not AND, Parallel PMOS, Series NMOS"

Question 2(b) OR [4 marks]

Explain operating mode and VTC of Resistive load inverter circuit.

Answer:

Circuit Configuration:

goat

Operating Modes:

VTC Characteristics:

• VOH: Excellent (VDD)
• VOL: Depends on R and RDS ratio
• Power consumption: Static current when input high
• Transition: Gradual due to resistive load

Design Trade-offs:

• Large R: Better VOL, slower switching
• Small R: Faster switching, higher power
• Area: Resistor occupies significant space

Mnemonic: "RLI - Resistive Load has Inevitable power consumption"

Question 2(c) OR [7 marks]

Draw CMOS inverter and explain its operation with VTC.

Answer:

CMOS Inverter Circuit:

goat

Operation Regions:

VTC Analysis:

goat

Key Features:

• Zero static power: No DC current path
• Full swing: VOH = VDD, VOL = 0V
• High noise margins: NMH = NML ≈ 0.4VDD
• Sharp transition: High gain in transition region

Design Considerations:

• β ratio: βN/βP for symmetric switching
• Threshold matching: VTN ≈ |VTP| preferred

Mnemonic: "CMOS has Zero Static Power with Full Swing"

Question 3(a) [3 marks]

Realize Y= (A̅+B̅)C̅+D̅+E̅ using depletion load.

Answer:

Logic Simplification: Y = (A̅+B̅)C̅+D̅+E̅ = A̅C̅+B̅C̅+D̅+E̅

Depletion Load Implementation:

goat

Pull-down Network:

• Series: A̅C̅ path and B̅C̅ path
• Parallel: All paths connected in parallel
• Implementation: Requires proper transistor sizing

Mnemonic: "Depletion Load with Parallel pull-down Paths"

Question 3(b) [4 marks]

Write a short note on FPGA.

Answer:

FPGA Definition: Field Programmable Gate Array - Reconfigurable integrated circuit.

Architecture Components:

Programming Technologies:

• SRAM-based: Volatile, fast reconfiguration
• Antifuse: Non-volatile, one-time programmable
• Flash-based: Non-volatile, reprogrammable

Applications:

• Prototyping: Digital system development
• DSP: Signal processing applications
• Control systems: Industrial automation
• Communications: Protocol implementation

Advantages vs ASIC:

• Flexibility: Reconfigurable design
• Time-to-market: Faster development
• Cost: Lower for small volumes
• Risk: Reduced design risk

Mnemonic: "FPGA - Flexible Programming Gives Advantages"

Question 3(c) [7 marks]

Draw and explain Y chart design flow.

Answer:

Y-Chart Diagram:

Design Domains:

Design Flow Process:

• Top-down: Start from behavioral, move to physical
• Bottom-up: Build from components upward
• Mixed approach: Combination of both methods

Abstraction Levels:

• System level: Highest abstraction
• RT level: Register transfer operations
• Gate level: Boolean logic implementation
• Layout level: Physical geometry

Design Verification:

• Horizontal: Between domains at same level
• Vertical: Between levels in same domain

Mnemonic: "Y-Chart: Behavioral, Structural, Physical - BSP domains"

Question 3(a) OR [3 marks]

Explain NOR2 gate using depletion load.

Answer:

Depletion Load NOR2 Circuit:

goat

Truth Table:

Operation:

• Both inputs low: Both NMOS OFF, Y = VDD
• Any input high: Corresponding NMOS ON, Y = VOL
• Load transistor: Provides pull-up current

Mnemonic: "NOR with Depletion - Parallel NMOS pull-down"

Question 3(b) OR [4 marks]

Compare full custom and semi-custom design styles.

Answer:

Comparison Table:

Full Custom Characteristics:

• Every transistor: Manually designed and placed
• Layout optimization: Maximum density achieved
• Applications: High-volume, performance-critical

Semi-Custom Types:

• Gate Array: Pre-defined transistor array
• Standard Cell: Library of pre-designed cells
• FPGA: Field programmable logic

Design Flow Comparison:

• Full Custom: Specification → Schematic → Layout → Verification
• Semi-Custom: Specification → HDL → Synthesis → Place & Route

Mnemonic: "Full Custom - Maximum control, Semi-Custom - Speed compromise"

Question 3(c) OR [7 marks]

Draw and explain ASIC design flow in detail.

Answer:

ASIC Design Flow:

Design Stages:

Verification Steps:

• Functional: RTL simulation and verification
• Gate-level: Post-synthesis simulation
• Physical: DRC, LVS, antenna checks
• Timing: STA for setup/hold violations

Design Constraints:

• Timing: Clock frequency requirements
• Area: Silicon area limitations
• Power: Power consumption targets
• Test: Design for testability

Sign-off Checks:

• DRC: Design Rule Check
• LVS: Layout Versus Schematic
• STA: Static Timing Analysis
• Power: Power integrity analysis

Mnemonic: "ASIC flow: RTL → Synthesis → Physical → Verification"

Question 4(a) [3 marks]

Implement the logic function G = (A(D+E)+BC)̅ using CMOS

Answer:

Logic Analysis: G = (A(D+E)+BC)̅ = (AD+AE+BC)̅

CMOS Implementation:

goat

Network Configuration:

• PMOS: Series implementation of complement
• NMOS: Parallel implementation of original function

Mnemonic: "Complex CMOS - PMOS series, NMOS parallel"

Question 4(b) [4 marks]

Write a Verilog code for 3 bit parity checker.

Answer:

Verilog Code:

verilog

Truth Table:

Key Features:

• XOR reduction: ^data_in gives even parity
• Complement: ~(^data_in) gives odd parity

Mnemonic: "Parity Check: XOR all bits"

Question 4(c) [7 marks]

Implement: 1) G = (AD +BC+EF) using CMOS [3 marks] 2) Y' = (ABCD + EF(G+H)+ J) using CMOS [4 marks]

Answer:

Part 1: G = (AD +BC+EF) [3 marks]

CMOS Circuit:

goat

Part 2: Y' = (ABCD + EF(G+H)+ J) [4 marks]

This requires a complex implementation with multiple stages:

Stage 1: Implement (G+H) Stage 2: Implement EF(G+H)
Stage 3: Combine all terms

Simplified approach using transmission gates and multiple stages would be more practical for this complex function.

Mnemonic: "Complex functions need staged implementation"

Question 4(a) OR [3 marks]

Explain AOI logic with example.

Answer:

AOI Definition: AND-OR-Invert logic implements functions of form: Y = (AB + CD + ...)̅

Example: Y = (AB + CD)̅

AOI Implementation:

goat

Advantages:

• Single stage: Direct implementation
• Fast: No propagation through multiple levels
• Area efficient: Fewer transistors than separate gates

Applications:

• Complex gates: Multi-input functions
• Speed-critical paths: Reduced delay

Mnemonic: "AOI - AND-OR-Invert in one stage"

Question 4(b) OR [4 marks]

Write Verilog Code for 4-bit Serial IN Parallel out shift register.

Answer:

Verilog Code:

verilog

Testbench Example:

verilog

Operation Timeline:

Mnemonic: "SIPO - Serial In, Parallel Out with shift left"

Question 4(c) OR [7 marks]

Implement clocked NOR2 SR latch and D-latch using CMOS.

Answer:

Clocked NOR2 SR Latch:

goat

D-Latch Implementation:

goat

CMOS D-Latch Circuit:

goat

Operation:

• CLK = 1: Master transparent, slave holds
• CLK = 0: Master holds, slave transparent
• Data transfer: On clock edge

Truth Table for SR Latch:

Mnemonic: "Clocked latches use transmission gates for timing control"

Question 5(a) [3 marks]

Draw the stick diagram for Y = (PQ +U)' using CMOS considering Euler path approach.

Answer:

Logic Analysis: Y = (PQ + U)' requires PMOS: (PQ)' · U' = (P' + Q') · U' NMOS: PQ + U

Stick Diagram:

goat

Euler Path:

1. PMOS: P' → Q' (series), then parallel to U'
2. NMOS: P → Q (series), then parallel to U
3. Optimal routing: Minimizes crossovers

Layout Considerations:

• Diffusion breaks: Minimize for better performance
• Contact placement: Proper VDD/GND connections
• Metal routing: Avoid DRC violations

Mnemonic: "Stick diagram shows physical layout with Euler path optimization"

Question 5(b) [4 marks]

Implement 8×1 multiplexer using Verilog

Answer:

Verilog Code:

verilog

Alternative Implementation:

verilog

Truth Table:

Testbench:

verilog

Mnemonic: "MUX selects one of many inputs based on select lines"

Question 5(c) [7 marks]

Implement full adder using behavioral modeling style in Verilog.

Answer:

Verilog Code:

verilog

Alternative Behavioral Style:

verilog

Truth Table:

Testbench:

verilog

Behavioral Features:

• Always block: Describes behavior, not structure
• Case statement: Truth table implementation
• Automatic synthesis: Tools generate optimized circuit

Mnemonic: "Behavioral modeling describes what circuit does, not how"

Question 5(a) OR [3 marks]

Implement NOR2 gate CMOS circuit with its stick diagram.

Answer:

CMOS NOR2 Circuit:

goat

Stick Diagram:

goat

Layout Rules:

• PMOS: Parallel connection for pull-up
• NMOS: Series connection for pull-down
• Contacts: Proper VDD/GND connections
• Spacing: Meet minimum design rules

Mnemonic: "NOR gate: Parallel PMOS, Series NMOS"

Question 5(b) OR [4 marks]

Implement 4 bit up counter using Verilog

Answer:

Verilog Code:

verilog

Enhanced Version with Overflow:

verilog

Count Sequence:

Testbench:

verilog

Mnemonic: "Up counter: increment on each clock when enabled"

Question 5(c) OR [7 marks]

Implement 3:8 decoder using behavioral modeling style in Verilog.

Answer:

Verilog Code:

verilog

Alternative Implementation:

verilog

Truth Table:

Testbench:

verilog

Applications:

• Memory addressing: Select one of 8 memory locations
• Device selection: Enable one of 8 peripheral devices
• Demultiplexing: Route single input to selected output

Design Features:

• One-hot encoding: Only one output high at a time
• Enable control: Global enable/disable functionality
• Full decoding: All possible input combinations handled

Mnemonic: "3:8 Decoder - 3 inputs select 1 of 8 outputs"