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title: 'Lecture 18: Thermal Runaway, Thermal Resistance & Thermal Stability'
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  ## DI02011011: Electronics Circuit and Application (ECA)
  Transistor Biasing circuits And Thermal stability
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# DI02011011: Electronics Circuit and Application (ECA)
## Lecture 18: Thermal Runaway, Thermal Resistance & Thermal Stability
### Transistor Biasing circuits And Thermal stability

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Welcome to Lecture 18. Today we explore the thermal dynamics of power transistors. When a transistor dissipates power, junction temperature rises. If heat generation outpaces heat dissipation, positive thermal feedback causes destructive thermal runaway. We will derive the exact mathematical conditions to prevent this failure mode.
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# Lecture Blueprint: Thermal Mechanics & Stability

- Physical Mechanism & Positive Feedback Loop of Thermal Runaway.
- Junction Temperature Ratings ($T_{J,\max}$) & Silicon vs Germanium Package Limits.
- Quantitative Definition of Thermal Resistance ($\theta_{JA}, \theta_{JC}, \theta_{CS}, \theta_{SA}$).
- Electrical Circuit Analogy of Thermal Networks (Ohm's Law Analogy).
- Mathematical Derivation of Fundamental Thermal Stability Criterion $\frac{\partial P_D}{\partial T_J} < \frac{1}{\theta_{JA}}$.
- Derivation of the $V_{CE} \le \frac{1}{2}V_{CC}$ Rule for Self-Biased Amplifiers.
- Power Transistor Derating Curves & Numerical Calculation Worked Examples.

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We will move from thermal definitions to electrical equivalences, derive the thermal stability differential equation, prove the half-supply voltage rule, and work out real thermal calculations.
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# Physical Mechanism of Thermal Runaway in BJTs

- Power Dissipation at Collector Junction: $P_D = V_{CE} I_C + V_{BE} I_B \approx V_{CE} I_C$.
- The Self-Reinforcing Positive Feedback Loop: Temperature Rise ($T_J \uparrow$) $\implies$ Leakage Current Increase ($I_{CO} \uparrow$) $\implies$ Collector Current Rise ($I_C \uparrow$) $\implies$ Power Dissipation Increase ($P_D \uparrow$) $\implies$ Further Temperature Rise ($T_J \uparrow\uparrow$).
- Destructive Junction Melting: Unchecked junction temperature exceeding $T_{J,\max}$ ($150^\circ\text{C}-200^\circ\text{C}$ for Silicon) causes permanent lattice destruction, bond rupturing, and short-circuit failure.
- Dominant Risk Factors: High ambient temperatures, inadequate heat sinking, high collector voltages ($V_{CE} > \frac{1}{2} V_{CC}$), and fixed-bias circuit topologies.

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Thermal runaway occurs because collector current increases with temperature. Since power dissipation is $V_{CE} I_C$, higher temperature generates more heat. If heat removal cannot keep up, the device destroys itself.
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# Quantitative Definition of Thermal Resistance ($\theta$)

- Thermal Resistance Definition: $\theta \equiv \frac{\Delta T}{P_D} = \frac{T_1 - T_2}{P_D}$, measured in units of $^\circ\text{C/W}$ (degrees Celsius per watt).
- Junction-to-Case Resistance ($\theta_{JC}$): Internal thermal impedance between silicon die junction and package case; fixed by semiconductor manufacturer.
- Case-to-Sink Resistance ($\theta_{CS}$): Contact thermal impedance between transistor case and heat sink surface; dependent on thermal grease / mica washer mounting.
- Sink-to-Ambient Resistance ($\theta_{SA}$): Convective & radiative thermal impedance from heat sink to ambient air; dependent on fin surface area and air flow.
- Total Junction-to-Ambient Resistance: $\theta_{JA} = \theta_{JC} + \theta_{CS} + \theta_{SA}$.

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Thermal resistance quantifies resistance to heat flow. Just like electrical resistance is voltage over current, thermal resistance is temperature difference over dissipated power.
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# Electrical Circuit Analogy of Thermal Networks

- Thermal-Electrical Equivalence Parameters:
-   • Heat Dissipation Power $P_D$ (Watts) $\equiv$ Electrical Current $I$ (Amperes).
-   • Temperature $T$ ($^\circ\text{C}$ or $\text{K}$) $\equiv$ Electrical Voltage $V$ (Volts).
-   • Thermal Resistance $\theta$ ($^\circ\text{C/W}$) $\equiv$ Electrical Resistance $R$ (Ohms).
-   • Thermal Capacitance $C_{th}$ (Joules/$^\circ\text{C}$) $\equiv$ Electrical Capacitance $C$ (Farads).
- Fundamental Node Voltage Equation: $T_J - T_A = P_D \cdot \theta_{JA} = P_D \cdot (\theta_{JC} + \theta_{CS} + \theta_{SA})$.
- Equivalent Circuit Schematic: Current source $P_D$ flowing through series resistors $\theta_{JC}$, $\theta_{CS}$, $\theta_{SA}$ anchored to ground potential $T_A$.

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By mapping thermal systems to electrical equivalent circuits, we can use Ohm's Law ($V = I R \implies \Delta T = P_D \theta$) to solve complex multi-layer cooling problems easily.
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# Mathematical Derivation of Fundamental Thermal Stability Condition

- Heat Generation Rate: $P_D = f(T_J)$ (power dissipated by the junction as a function of temperature).
- Heat Dissipation Rate (Removal): $P_R = \frac{T_J - T_A}{\theta_{JA}}$ (power transferred to ambient atmosphere).
- Thermal Equilibrium Condition: At steady state, $P_D = P_R \implies T_J = T_A + P_D \theta_{JA}$.
- Stability Criterion against Thermal Perturbation: To prevent runaway, the rate of increase of heat generation must be LESS than the rate of increase of heat removal.
- Mathematical Inequality: $\frac{\partial P_D}{\partial T_J} < \frac{\partial P_R}{\partial T_J} \implies \frac{\partial P_D}{\partial T_J} < \frac{1}{\theta_{JA}}$.
- Physical Meaning: If $\frac{\partial P_D}{\partial T_J} \ge \frac{1}{\theta_{JA}}$, any infinitesimal temperature spike generates more heat than can be radiated, triggering runaway.

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This is the central derivation of thermal stability. The derivative $\frac{\partial P_D}{\partial T_J}$ represents the rate of internal heat generation. It must strictly remain below $1/\theta_{JA}$.
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# Collector Power Dissipation Derivative & Circuit Parameters

- Collector Power Dissipation: $P_D = V_{CE} I_C$.
- Chain Rule Expansion with respect to Junction Temperature $T_J$: $\frac{\partial P_D}{\partial T_J} = \frac{\partial (V_{CE} I_C)}{\partial T_J} = V_{CE} \frac{\partial I_C}{\partial T_J} + I_C \frac{\partial V_{CE}}{\partial T_J}$.
- Relating $V_{CE}$ to $I_C$ via KVL Loop: In a common emitter stage, $V_{CE} = V_{CC} - I_C (R_C + R_E) \implies \frac{\partial V_{CE}}{\partial I_C} = -(R_C + R_E)$.
- Substituting $\frac{\partial V_{CE}}{\partial T_J} = \frac{\partial V_{CE}}{\partial I_C} \frac{\partial I_C}{\partial T_J} = -(R_C + R_E) \frac{\partial I_C}{\partial T_J}$:
- Simplified Power Derivative: $\frac{\partial P_D}{\partial T_J} = V_{CE} \frac{\partial I_C}{\partial T_J} - I_C (R_C + R_E) \frac{\partial I_C}{\partial T_J} = \frac{\partial I_C}{\partial T_J} \left[ V_{CE} - I_C (R_C + R_E) \right]$.

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Substituting the KVL relationship between $V_{CE}$ and $I_C$ into the power derivative reveals how circuit resistor values $R_C$ and $R_E$ physically limit power dissipation growth.
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# Derivation of the Self-Bias Thermal Stability Condition ($V_{CE} \le \frac{1}{2} V_{CC}$)

- Expressing $I_C (R_C + R_E)$ from DC KVL: $I_C (R_C + R_E) = V_{CC} - V_{CE}$.
- Substitute into Power Derivative: $\frac{\partial P_D}{\partial T_J} = \frac{\partial I_C}{\partial T_J} \left[ V_{CE} - (V_{CC} - V_{CE}) \right] = \frac{\partial I_C}{\partial T_J} \left[ 2 V_{CE} - V_{CC} \right]$.
- Evaluating Condition for Negative or Zero Heat Derivative ($\frac{\partial P_D}{\partial T_J} \le 0$):
-   Since $\frac{\partial I_C}{\partial T_J} > 0$, we require $2 V_{CE} - V_{CC} \le 0 \implies V_{CE} \le \frac{1}{2} V_{CC}$.
- Engineering Consequence: When $V_{CE} < \frac{1}{2} V_{CC}$, any increase in $I_C$ due to temperature causes $V_{CE}$ to decrease so rapidly that total power $P_D = V_{CE} I_C$ ACTUALLY DECREASES! Thermal runaway becomes physically impossible.

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This is a profound result in transistor electronics. If $V_{CE} \le 0.5 V_{CC}$, an increase in collector current drops $V_{CE}$ so much that total power dissipation drops. Heat generation becomes self-limiting!
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# Power Transistor Derating Curves & Maximum Dissipation

- Maximum Power Dissipation Rating ($P_{D,\max}$): Datasheet power rating specified at case temperature $T_C = 25^\circ\text{C}$, given by $P_{D,\max}(25^\circ\text{C}) = \frac{T_{J,\max} - 25^\circ\text{C}}{\theta_{JC}}$.
- Thermal Derating Region ($T_C > 25^\circ\text{C}$): As case/ambient temperature increases, allowable power dissipation decreases linearly to zero at $T_{J,\max}$.
- Power Derating Equation: $P_{D,\max}(T_A) = \frac{T_{J,\max} - T_A}{\theta_{JA}} = \frac{T_{J,\max} - T_A}{\theta_{JC} + \theta_{CS} + \theta_{SA}}$.
- Derating Slope Factor: $\text{Derating Factor} = \frac{1}{\theta_{JA}} \,\text{(in W/}^\circ\text{C)}$.
- Safe Operating Area (SOA): Enforces simultaneous constraints on maximum voltage $V_{CE,\max}$, peak current $I_{C,\max}$, thermal power dissipation limit $P_{D,\max}$, and secondary breakdown boundary.

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Transistors cannot dissipate their rated maximum power at elevated temperatures. The power derating curve defines the reduced allowable dissipation as temperature rises.
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# Transient Thermal Impedance & Pulse Power Handling

- Thermal Mass & Heat Capacity: Semiconductor die and copper headers possess thermal capacitance $C_{th} = m \cdot c_p$ (Joules/$^\circ\text{C}$).
- Transient Thermal Impedance $Z_{\theta JA}(t)$: For short power pulses ($t_p \ll \tau_{th}$), the effective thermal resistance is significantly lower than steady-state $\theta_{JA}$.
- Thermal Time Constant: $\tau_{th} = \theta_{JA} \cdot C_{th}$. Typical die time constants range from $100\,\mu\text{s}$ to $10\,\text{ms}$, while heat sinks range from $10\,\text{s}$ to $100\,\text{s}$.
- Pulsed Power Application: Allows power transistors to handle transient peak power pulses (e.g. 500W for 1ms) far exceeding their continuous DC power rating (e.g. 50W).

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During brief transient pulses, thermal capacitance absorbs heat before temperatures can rise, allowing peak power handling far above continuous DC limits.
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# Role of Emitter Resistor $R_E$ and Stability Factor $S$ in Preventing Thermal Runaway

- Collector Current Temperature Derivative: $\frac{\partial I_C}{\partial T_J} = S \cdot \frac{\partial I_{CO}}{\partial T_J} + S' \cdot \frac{\partial V_{BE}}{\partial T_J} + S'' \cdot \frac{\partial \beta}{\partial T_J}$.
- Impact of Stability Factor $S$: Minimizing $S$ directly reduces $\frac{\partial I_C}{\partial T_J}$.
- Evaluating Thermal Runaway Criterion: $\left( S \frac{\partial I_{CO}}{\partial T_J} + S' \frac{\partial V_{BE}}{\partial T_J} \right) (2 V_{CE} - V_{CC}) < \frac{1}{\theta_{JA}}$.
- Emitter Resistor Degeneration: Adding $R_E$ increases total loop resistance $(R_C + R_E)$ and reduces $S$, providing dual protection against thermal runaway.
- Design Summary: Achieving thermal stability requires both appropriate electrical bias design ($S \le 5$) and proper physical thermal dissipation design ($\theta_{SA}$ sizing).

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Thermal stability is an integrated electro-thermal problem. Emitter resistor $R_E$ improves both electrical stability factor $S$ and physical thermal stability.
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# Numerical Example: Junction Temperature & Power Rating Calculation

- Given Parameters: Silicon power transistor with $T_{J,\max} = 175^\circ\text{C}$, $\theta_{JC} = 1.5^\circ\text{C/W}$. Mounted on heat sink with thermal washer $\theta_{CS} = 0.5^\circ\text{C/W}$ and heat sink rating $\theta_{SA} = 2.0^\circ\text{C/W}$. Ambient temperature $T_A = 40^\circ\text{C}$. Transistor dissipates $P_D = 30\,\text{W}$.
- Step 1: Calculate Total Thermal Resistance $\theta_{JA}$: $\theta_{JA} = \theta_{JC} + \theta_{CS} + \theta_{SA} = 1.5 + 0.5 + 2.0 = 4.0^\circ\text{C/W}$.
- Step 2: Calculate Operating Junction Temperature $T_J$: $T_J = T_A + P_D \cdot \theta_{JA} = 40^\circ\text{C} + (30\,\text{W} \times 4.0^\circ\text{C/W}) = 40^\circ\text{C} + 120^\circ\text{C} = 160^\circ\text{C}$.
- Step 3: Evaluate Safety Margin: $T_J = 160^\circ\text{C} < T_{J,\max} = 175^\circ\text{C}$. The design operates safely with a $15^\circ\text{C}$ thermal headroom.
- Step 4: Calculate Maximum Allowable Power at $T_A = 40^\circ\text{C}$: $P_{D,\max} = \frac{175 - 40}{4.0} = \frac{135}{4.0} = 33.75\,\text{W}$.

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Let's work through this step-by-step thermal calculation. We sum the series thermal resistances to find total $\theta_{JA} = 4.0^\circ\text{C/W}$ and compute $T_J = 160^\circ\text{C}$.
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# Numerical Example: Thermal Runaway Threshold Determination

- Given Circuit: BJT biased at $V_{CC} = 24\,\text{V}$, $V_{CE} = 16\,\text{V}$, $I_C = 1.5\,\text{A}$. $R_C + R_E = 5.33\,\Omega$. Total thermal resistance $\theta_{JA} = 3.0^\circ\text{C/W}$. Measured collector current drift rate $\frac{\partial I_C}{\partial T_J} = 12\,\text{mA/}^\circ\text{C} = 0.012\,\text{A/}^\circ\text{C}$.
- Step 1: Check $V_{CE}$ relative to $\frac{1}{2}V_{CC}$: $\frac{1}{2}V_{CC} = 12\,\text{V}$. Since $V_{CE} = 16\,\text{V} > 12\,\text{V}$, $\frac{\partial P_D}{\partial T_J} > 0$ and thermal runaway is POSSIBLY RISKY.
- Step 2: Calculate Power Dissipation Derivative $\frac{\partial P_D}{\partial T_J}$: $\frac{\partial P_D}{\partial T_J} = \frac{\partial I_C}{\partial T_J} (2 V_{CE} - V_{CC}) = 0.012\,\text{A/}^\circ\text{C} \times (2(16) - 24) = 0.012 \times (32 - 24) = 0.096\,\text{W/}^\circ\text{C}$.
- Step 3: Calculate Heat Dissipation Capability $\frac{1}{\theta_{JA}}$: $\frac{1}{\theta_{JA}} = \frac{1}{3.0^\circ\text{C/W}} = 0.333\,\text{W/}^\circ\text{C}$.
- Step 4: Test Thermal Stability Inequality: $\frac{\partial P_D}{\partial T_J} = 0.096\,\text{W/}^\circ\text{C} < \frac{1}{\theta_{JA}} = 0.333\,\text{W/}^\circ\text{C}$.
- Conclusion: The system is THERMALLY STABLE because heat removal capability ($0.333\,\text{W/}^\circ\text{C}$) exceeds internal heat generation growth ($0.096\,\text{W/}^\circ\text{C}$).

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Even though $V_{CE} > 0.5 V_{CC}$, the system remains stable because the internal power derivative of 0.096 W/°C is well below the heat sink dissipation limit of 0.333 W/°C.
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# Summary & Core Principles of Thermal Design

- Thermal Runaway Mechanism: Uncontrolled thermal feedback loop driven by exponential $I_{CO}$ and $V_{BE}$ thermal drift.
- Thermal Resistance Network: Junction temperature $T_J = T_A + P_D (\theta_{JC} + \theta_{CS} + \theta_{SA})$.
- Universal Stability Criterion: Must enforce $\frac{\partial P_D}{\partial T_J} < \frac{1}{\theta_{JA}}$ under all operating conditions.
- Half-Supply Voltage Rule: Biasing at $V_{CE} \le \frac{1}{2} V_{CC}$ makes $\frac{\partial P_D}{\partial T_J} \le 0$, rendering thermal runaway physically impossible.
- Integrated Design Strategy: Combine electrical bias stabilization ($S \le 5$) with properly sized heat sinking (low $\theta_{SA}$) to guarantee lifetime reliability.

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To summarize: control junction temperature by calculating series thermal resistance, ensure $V_{CE} \le 0.5 V_{CC}$ when possible, and size heat sinks properly. Next lecture: Heat Sinks and Cooling Topologies.
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