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title: 'Lecture 14: The Load Lines: D'
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  ## DI02011011: Electronics Circuit and Application (ECA)
  Transistor Biasing circuits And Thermal stability
---

# DI02011011: Electronics Circuit and Application (ECA)
## Lecture 14: The Load Lines: D
### Transistor Biasing circuits And Thermal stability

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Welcome to Lecture 14. Today we advance our load line analysis to evaluate dynamic signal power, collector junction power dissipation, and power conversion efficiency. We will derive the maximum theoretical $25\%$ efficiency for series-fed Class-A amplifiers and analyze dynamic Q-point shifts under large signal conditions.
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# Lecture Plan: Dynamic Design & Power Efficiency

- Dynamic Load Line Mechanics across Transistor Configurations (CE, CC, CB)
- AC Collector Power Output Calculation ($P_{ac}$)
- DC Supply Power ($P_{dc}$) and Transistor Collector Dissipation ($P_C$)
- Derivation of Series-Fed Class-A Amplifier Efficiency ($\eta = P_{ac}/P_{dc}$)
- Transformer-Coupled Class-A Load Lines and Efficiency Limit ($50\%$)
- Dynamic Q-Point Shift under Large-Signal Overdrive
- Thermal Hyperbola and Transistor Power Dissipation Ratings ($P_{D(\max)}$)
- Design Problem 1: Designing Biasing for Target AC Power Output
- Design Problem 2: Symmetrical Swing Optimization with Real-World Tolerances
- Summary & Practical Engineering Principles

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Our agenda for Lecture 14 focuses on dynamic AC signal power, DC supply power, conversion efficiency, transformer coupling, thermal hyperbolas, and solving two practical amplifier design problems.
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# Dynamic Load Lines Across BJT Configurations

- Common-Emitter (CE) Configuration: Highest combined voltage and current gain. DC load resistance $R_{DC} = R_C + R_E$, AC load resistance $r_c = R_C \parallel R_L$. High input impedance, inverted output AC phase ($180^\circ$).
- Common-Collector (CC / Emitter Follower): Unity voltage gain ($A_v \approx 1$), high current gain ($\beta + 1$). Collector tied to DC supply ($R_C = 0$). Load resistor $R_L$ is placed in emitter circuit. $R_{DC} = R_E$, $r_e = R_E \parallel R_L$. AC load line equation: $i_e - I_{EQ} = -\frac{1}{r_e}(v_{ce} - V_{CEQ})$.
- Common-Base (CB) Configuration: High voltage gain, unity current gain ($\alpha \approx 1$). Low input impedance, high output impedance. Used in high-frequency RF amplification. $R_{DC} = R_C + R_E$, $r_c = R_C \parallel R_L$.

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Load lines apply to all three BJT configurations. In an Emitter Follower (CC), $R_C = 0$ and the load $R_L$ is in the emitter circuit, so the AC load line slope is $-1/(R_E \parallel R_L)$. In Common-Base, load lines govern high-frequency RF power output.
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# AC Power Output Derivation ($P_{ac}$)

- RMS Signal Quantities: For a sinusoidal AC signal, RMS voltage across load $r_c$ is $V_{ce(rms)} = \frac{V_{ce(peak)}}{\sqrt{2}}$ and RMS current is $I_{c(rms)} = \frac{I_{c(peak)}}{\sqrt{2}}$.
- AC Power Delivered to Load Resistance ($P_{ac}$): $P_{ac} = V_{ce(rms)} \cdot I_{c(rms)} = \frac{V_{ce(peak)}}{\sqrt{2}} \cdot \frac{I_{c(peak)}}{\sqrt{2}} = \frac{V_{ce(peak)} \cdot I_{c(peak)}}{2}$.
- Peak-to-Peak Expression: Expressing in terms of peak-to-peak voltage $V_{o(p-p)}$ and current $I_{o(p-p)}$: $P_{ac} = \frac{V_{o(p-p)} \cdot I_{o(p-p)}}{8} = \frac{V_{o(p-p)}^2}{8 r_c}$.
- Maximum Unclipped AC Power Output: Under maximum unclipped symmetrical swing condition ($V_{ce(peak)} = V_{CEQ}, I_{c(peak)} = I_{CQ}$): $P_{ac(\max)} = \frac{V_{CEQ} \cdot I_{CQ}}{2}$.

<!--
To calculate AC power delivered by the amplifier, we use RMS values. $P_{ac} = V_{ce(rms)} I_{c(rms)} = \frac{V_{ce(peak)} I_{c(peak)}}{2} = \frac{V_{o(p-p)}^2}{8 r_c}$. The maximum unclipped power occurs when signal peaks reach $V_{CEQ}$ and $I_{CQ}$.
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# DC Power Supply & Collector Dissipation

- Total DC Power Input ($P_{dc}$): Supplied by the DC voltage source $V_{CC}$ to the entire amplifier circuit: $P_{dc} = V_{CC} \cdot I_{CC} \approx V_{CC} \cdot I_{CQ}$ (neglecting minor base bias current).
- DC Power Dissipated in Resistors ($P_R$): Power consumed as heat in collector and emitter resistors: $P_R = I_{CQ}^2 (R_C + R_E) = I_{CQ}^2 R_{DC}$.
- Collector Junction Power Dissipation ($P_C$): Under zero AC signal conditions, transistor collector junction absorbs all remaining DC power: $P_{C(\text{quiescent})} = V_{CEQ} \cdot I_{CQ}$.
- Signal-Dependent Collector Power ($P_C(ac)$): When AC signal is present, AC power $P_{ac}$ is delivered to load, REDUCING transistor heating: $P_C = P_{C(\text{quiescent})} - P_{ac}$.
- Worst-Case Thermal Condition: Maximum transistor heating occurs at ZERO AC INPUT SIGNAL ($v_{in} = 0$), where $P_C = V_{CEQ} \cdot I_{CQ}$.

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A critical rule of Class-A amplifiers: The transistor runs HOTTEST when NO AC signal is playing! Under zero signal, $P_C = V_{CEQ} I_{CQ}$. When an AC signal is applied, part of the DC power is converted into useful AC power delivered to the load, reducing heating inside the transistor.
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# Derivation of Max Efficiency for Series-Fed Class-A

- Power Conversion Efficiency Definition: Efficiency $\eta$ measures the capability of an amplifier to convert DC supply power into useful AC signal power: $\eta = \frac{P_{ac}}{P_{dc}} \times 100\%$.
- Series-Fed Configuration: Load resistor is directly connected as the collector resistor ($R_C = R_L$, $R_{DC} = r_c = R_C$).
- DC Load Line Endpoints: Saturation $I_{C(\text{sat})} = \frac{V_{CC}}{R_C}$, Cutoff $V_{CE(\text{off})} = V_{CC}$.
- Optimum Q-Point for Max Swing: $V_{CEQ} = \frac{V_{CC}}{2}$ and $I_{CQ} = \frac{V_{CC}}{2 R_C}$.
- Max AC Power Output: $P_{ac(\max)} = \frac{V_{CEQ} \cdot I_{CQ}}{2} = \frac{(V_{CC}/2)(V_{CC}/2 R_C)}{2} = \frac{V_{CC}^2}{8 R_C}$.
- Total DC Power Input: $P_{dc} = V_{CC} \cdot I_{CQ} = V_{CC} \cdot \frac{V_{CC}}{2 R_C} = \frac{V_{CC}^2}{2 R_C}$.
- Efficiency Derivation: $\eta_{\max} = \frac{P_{ac(\max)}}{P_{dc}} = \frac{V_{CC}^2 / 8 R_C}{V_{CC}^2 / 2 R_C} = \frac{2}{8} = 0.25 = 25\%$.

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Here is the classic proof for maximum efficiency of a series-fed Class-A amplifier. At maximum symmetrical swing, $P_{ac(\max)} = V_{CC}^2 / 8R_C$ while $P_{dc} = V_{CC}^2 / 2R_C$. Dividing $P_{ac}$ by $P_{dc}$ gives exactly $0.25$ or $25\%$. The remaining $75\%$ of supply power is wasted as heat!
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# Transformer-Coupled Class-A Amplifier Load Line

- Topology Advantage: Replacing collector resistor $R_C$ with a step-down transformer primary winding reduces DC collector resistance to near zero ($R_{DC} \approx 0\ \Omega$).
- DC Load Line Behavior: Since $R_{DC} \approx 0$, the DC load line is nearly VERTICAL at $V_{CEQ} \approx V_{CC}$.
- Reflected AC Load Resistance ($r_c'$): Impedance transformation by transformer turns ratio $n = N_1/N_2$: $r_c' = n^2 R_L = \left(\frac{N_1}{N_2}\right)^2 R_L$.
- AC Load Line Voltage Induction: Primary winding inductance allows collector voltage to swing UP TO TWICE $V_{CC}$ ($v_{ce(\text{off})} \approx 2 V_{CC}$) during negative current swings due to inductive kickback.
- Efficiency Derivation: Max AC swing $V_{ce(peak)} = V_{CC}$ and $I_{c(peak)} = I_{CQ}$. $P_{ac(\max)} = \frac{V_{CC} I_{CQ}}{2}$, $P_{dc} = V_{CC} I_{CQ}$. Efficiency $\eta_{\max} = \frac{V_{CC} I_{CQ} / 2}{V_{CC} I_{CQ}} = 50\%$.

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How can we double Class-A efficiency to $50\%$? By using a transformer! The primary winding has zero DC resistance ($R_{DC} \approx 0$), so $V_{CEQ} = V_{CC}$. Under AC signal conditions, magnetic energy in the primary induces an AC voltage that swings up to $2 V_{CC}$, doubling $P_{ac}$ and boosting maximum efficiency to $50\%$.
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# The Maximum Thermal Power Dissipation Hyperbola

- Transistor Rating Limits: Manufacturers specify maximum junction power rating $P_{D(\max)}$ at ambient temperature $25^\circ\text{C}$ (e.g., $500\text{ mW}$ for 2N2222, $10\text{ W}$ for TIP31).
- Thermal Hyperbola Equation: Plotting $V_{CE} \cdot I_C = P_{D(\max)}$ on output characteristics yields a rectangular hyperbola curve.
- Safe Operating Area (SOA): The region under the hyperbola bounded by $V_{CE(\max)}$ breakdown voltage and $I_{C(\max)}$ saturation current.
- Q-Point Boundary Constraint: To prevent transistor destruction from overheating, the quiescent Q-point MUST lie strictly BELOW the $P_{D(\max)}$ hyperbola curve.
- Derating Factor: At higher operating temperatures ($T_A > 25^\circ\text{C}$), $P_{D(\max)}$ must be derated linearly using thermal resistance $\theta_{JA}$: $P_{D(\text{derated})} = \frac{T_{j(\max)} - T_A}{\theta_{JA}}$.

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To protect transistors from burning out, we draw the Maximum Power Dissipation Hyperbola on the $I_C$ vs $V_{CE}$ graph ($V_{CE} \cdot I_C = P_{D(\max)}$). The Q-point must ALWAYS sit inside the safe operating area beneath this hyperbola.
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# Dynamic Q-Point Shift Under Large Signal Overdrive

- Small-Signal Assumption: Linear AC analysis assumes small input amplitudes where operating point variations remain strictly linear along the static AC load line.
- Large-Signal Non-Linearity: BJT exponential transconductance $I_C = I_S e^{V_{BE}/V_T}$ causes positive half-cycles of collector current to expand more than negative half-cycles contract.
- DC Average Shift: Non-symmetrical current peaks create a net DC rectified current component $\Delta I_{DC}$. Total average collector current becomes $I_{C(\text{avg})} = I_{CQ} + \Delta I_{DC}$.
- Dynamic Q-Point Migration: As input signal amplitude increases, the effective average Q-point shifts upward and rightward along the DC load line, altering bias conditions and increasing heat dissipation.

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What happens when we overdrive an amplifier with large signals? Because of the exponential $I_C-V_{BE}$ curve, positive current peaks are larger than negative peaks. This asymmetry creates a net DC current shift $\Delta I_{DC}$ that pulls the average operating point upward along the DC load line.
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# Worked Example: Power Dissipation & Efficiency Calculation

- Problem Statement: A Common-Emitter series-fed Class-A amplifier operates with $V_{CC} = 18\text{ V}$, collector resistor $R_C = 1.2\text{ k}\Omega$, and Q-point set at $V_{CEQ} = 9\text{ V}$, $I_{CQ} = 7.5\text{ mA}$.
1. Calculate DC supply power $P_{dc}$.
2. Calculate maximum unclipped AC power output $P_{ac(\max)}$.
3. Calculate amplifier conversion efficiency $\eta$.
4. Calculate transistor collector dissipation under zero signal $P_{C(0)}$ and max signal $P_{C(\max\text{ signal})}$.
- Step 1 (DC Power Input): $P_{dc} = V_{CC} \cdot I_{CQ} = 18\text{ V} \times 7.5\text{ mA} = 135\text{ mW}$.
- Step 2 (Max AC Power Output): $P_{ac(\max)} = \frac{V_{CEQ} \cdot I_{CQ}}{2} = \frac{9\text{ V} \times 7.5\text{ mA}}{2} = \frac{67.5}{2} = 33.75\text{ mW}$.
- Step 3 (Conversion Efficiency): $\eta = \frac{P_{ac(\max)}}{P_{dc}} \times 100\% = \frac{33.75\text{ mW}}{135\text{ mW}} \times 100\% = 25.0\%$.
- Step 4 (Transistor Heat Dissipation):
- Zero Signal: $P_{C(0)} = V_{CEQ} \cdot I_{CQ} = 9\text{ V} \times 7.5\text{ mA} = 67.5\text{ mW}$.
- Max Signal: $P_{C(\max\text{ signal})} = P_{C(0)} - P_{ac(\max)} = 67.5\text{ mW} - 33.75\text{ mW} = 33.75\text{ mW}$.

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Let's work through this power example. DC supply power is $135\text{ mW}$, max AC output power is $33.75\text{ mW}$, giving an exact $25\%$ efficiency. Notice that transistor heating drops from $67.5\text{ mW}$ at zero signal down to $33.75\text{ mW}$ at full AC output power!
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# Worked Example: Dynamic AC Load Line with External Load $R_L$

- Circuit Specification: $V_{CC} = 12\text{ V}$, $R_C = 2.2\text{ k}\Omega$, $R_E = 680\ \Omega$, $R_L = 1.0\text{ k}\Omega$, Q-point set at $I_{CQ} = 2.5\text{ mA}$, $V_{CEQ} = 4.8\text{ V}$.
- Step 1 (DC Resistance & DC Load Line Endpoints):
$R_{DC} = R_C + R_E = 2.2\text{ k}\Omega + 0.68\text{ k}\Omega = 2.88\text{ k}\Omega$.
DC Cutoff: $V_{CE(\text{off})} = 12\text{ V}$; DC Saturation: $I_{C(\text{sat})} = \frac{12\text{ V}}{2.88\text{ k}\Omega} = 4.167\text{ mA}$.
- Step 2 (AC Load Resistance $r_c$):
$r_c = R_C \parallel R_L = \frac{2.2 \times 1.0}{2.2 + 1.0}\text{ k}\Omega = \frac{2.2}{3.2}\text{ k}\Omega = 687.5\ \Omega$.
- Step 3 (AC Load Line Endpoints):
AC Saturation Current: $i_{C(\text{sat})} = I_{CQ} + \frac{V_{CEQ}}{r_c} = 2.5\text{ mA} + \frac{4.8\text{ V}}{687.5\ \Omega} = 2.5\text{ mA} + 6.982\text{ mA} = 9.482\text{ mA}$.
AC Cutoff Voltage: $v_{ce(\text{off})} = V_{CEQ} + I_{CQ} r_c = 4.8\text{ V} + (2.5\text{ mA} \times 687.5\ \Omega) = 4.8\text{ V} + 1.719\text{ V} = 6.519\text{ V}$.
- Step 4 (Max AC Power Delivered to Load $R_L$):
Max peak voltage across load: $V_{p} = \min(V_{CEQ} - V_{CE(\text{sat})}, I_{CQ} r_c) = \min(4.6\text{ V}, 1.719\text{ V}) = 1.719\text{ V}$.
AC Power to $R_L$: $P_{L(\max)} = \frac{V_p^2}{2 R_L} = \frac{(1.719)^2}{2 \times 1000} = \frac{2.955}{2000} = 1.478\text{ mW}$.

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In this example with external load $R_L = 1\text{ k}\Omega$, $r_c = 687.5\ \Omega$. The AC cutoff voltage is $6.52\text{ V}$, restricting max peak signal swing to $1.72\text{ V}$ before cutoff clipping occurs. The power delivered specifically to external load $R_L$ is $1.48\text{ mW}$.
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# Symmetrical Swing Design Optimization Procedure

- Objective: Given supply voltage $V_{CC}$ and AC load $R_L$, design $R_C$ and $R_E$ to achieve maximum symmetrical undistorted output voltage swing.
- Design Step 1: Choose emitter resistor drop $V_E \approx 0.1 V_{CC}$ for DC thermal stability. Set $R_E = \frac{0.1 V_{CC}}{I_{CQ}}$.
- Design Step 2: Set optimum $V_{CEQ}$ condition: $V_{CEQ(\text{opt})} = \frac{V_{CC} \cdot r_c}{r_c + R_{DC}}$.
- Design Step 3: Solve for required collector resistor $R_C$ such that $r_c = R_C \parallel R_L$ satisfies symmetrical swing $I_{CQ} r_c = V_{CEQ} - V_{CE(\text{sat})}$.
- Design Step 4: Verify that peak transistor dissipation $P_{C(0)} = V_{CEQ} I_{CQ}$ stays safely below $P_{D(\max)}$ thermal hyperbola with a $50\%$ safety margin.

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Here is the systematic 4-step procedure for designing symmetrical swing amplifiers. We start by fixing $V_E = 0.1 V_{CC}$, then match $I_{CQ} r_c = V_{CEQ}$, solve for $R_C$, and verify power dissipation against the thermal hyperbola.
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# Summary Table: Power & Load Line Formulas

- Core Formula Summary:
1. DC Load Line: $I_C = -\frac{1}{R_C+R_E} V_{CE} + \frac{V_{CC}}{R_C+R_E}$
2. AC Load Line: $i_C - I_{CQ} = -\frac{1}{r_c}(v_{CE} - V_{CEQ})$, where $r_c = R_C \parallel R_L$
3. AC Saturation Current: $i_{C(\text{sat})} = I_{CQ} + \frac{V_{CEQ}}{r_c}$
4. AC Cutoff Voltage: $v_{ce(\text{off})} = V_{CEQ} + I_{CQ} r_c$
5. Max Sinusoidal AC Power: $P_{ac(\max)} = \frac{V_{ce(peak)} I_{c(peak)}}{2} = \frac{V_{o(p-p)}^2}{8 r_c}$
6. DC Input Power: $P_{dc} = V_{CC} I_{CQ}$
7. Max Series-Fed Efficiency: $\eta_{\max} = 25\%$
8. Max Transformer-Coupled Efficiency: $\eta_{\max} = 50\%$

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This summary slide consolidates all essential formulas from Lectures 13 and 14. Keep these equations handy for solving complex multi-stage amplifier design problems.
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# Summary of Lecture 14 & Engineering Principles

- AC Power & Headroom: $P_{ac} = \frac{V_{ce(peak)} I_{c(peak)}}{2}$. AC swing is strictly bounded by load line intercepts $i_{C(\text{sat})}$ and $v_{ce(\text{off})}$.
- Class-A Efficiency Limits: Series-fed topology reaches a maximum of $25\%$ efficiency; transformer coupling elevates efficiency to $50\%$.
- Worst-Case Thermal Loading: Transistors dissipate maximum heat at ZERO AC input signal ($P_C = V_{CEQ} I_{CQ}$).
- Safe Operating Area: Q-point must remain below the thermal hyperbola $V_{CE} I_C = P_{D(\max)}$ under all operating temperatures.
- Next Lecture Preview: Transition to detailed analysis of BJT Biasing Methods (Fixed Bias, Collector Feedback, Emitter Bias, Voltage Divider Bias).

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To conclude Lecture 14: We mastered power calculations on dynamic AC load lines, derived efficiency limits for Class-A amplifiers, and established thermal hyperbola constraints. Next in Lecture 15, we will systematically compare all BJT Biasing Methods.
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