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title: 'Lecture 7: Enhancement type MOSFET'
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  ## DI02011011: Electronics Circuit and Application (ECA)
  Field Effect Transistors(FETs)
---

# DI02011011: Electronics Circuit and Application (ECA)
## Lecture 7: Enhancement type MOSFET
### Field Effect Transistors(FETs)

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Welcome to Lecture 7. Today we study the Enhancement-Type MOSFET, the foundational building block of modern digital logic, VLSI microprocessors, and power electronics. Unlike depletion devices, E-MOSFETs have no built-in channel and are strictly normally-OFF.
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# Lecture Outline: Enhancement MOSFET Structural Physics

- Physical Architecture of N-Channel and P-Channel E-MOSFETs.
- The MOS Structure & Gate Dielectric Breakdown limits.
- Electrostatic Surface States: Accumulation, Depletion, and Inversion Regimes.
- Mathematical Definition of Threshold Voltage ($V_{Th}$).
- Channel Formation Mechanics & Electron Inversion Layer Density.
- Standard Circuit Symbols for NMOS and PMOS Devices.
- Basic Conduction Thresholds & Quantitative Introductory Examples.

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Our agenda covers physical construction, metal-oxide-semiconductor electrostatics, threshold voltage derivation, inversion layer formation, schematic representations, and numerical examples.
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# Physical Architecture of N-Channel Enhancement MOSFET (NMOS)

- Substrate Foundation: Fabricated on a lightly doped P-type silicon substrate ($p$-substrate, doping concentration $N_A \approx 10^{15} \text{ cm}^{-3}$).
- Source and Drain Diffusions: Two heavily doped, isolated $n^+$ regions ($N_D \approx 10^{20} \text{ cm}^{-3}$) diffused into the $p$-substrate, separated by channel length $L$.
- Absence of Physical Channel: No conductive $n$-type region exists between source and drain at thermal equilibrium ($V_{GS} = 0\text{V}$).
- Gate Insulator: Thermally grown silicon dioxide layer ($SiO_2$, dielectric constant $\epsilon_{ox} = 3.9 \epsilon_0$) with oxide thickness $t_{ox} \approx 2\text{ nm}$ to $50\text{ nm}$.
- Gate Electrode & Contacts: Highly conductive heavily doped polysilicon or metal deposited on top of $SiO_2$, forming Gate (G), with metal contacts for Source (S), Drain (D), and Body (B).

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Examine the NMOS physical layout: the source and drain n+ regions are completely isolated from each other by the p-type substrate. Without an applied gate voltage, any attempt to pass current between drain and source faces back-to-back PN junctions, resulting in zero conduction.
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# Physical Architecture of P-Channel Enhancement MOSFET (PMOS)

- Substrate Foundation: Built on a lightly doped N-type silicon substrate ($n$-substrate, donor concentration $N_D \approx 10^{15} \text{ cm}^{-3}$).
- Source and Drain Diffusions: Two heavily doped, isolated $p^+$ wells ($N_A \approx 10^{20} \text{ cm}^{-3}$) implanted into the $n$-substrate.
- Dielectric Insulation: Oxide layer ($SiO_2$) insulates the gate electrode from the underlying $n$-substrate region between $p^+$ wells.
- Complementary Nature: Requires a negative gate-to-source voltage ($V_{GS} < V_{Th,p}$, where $V_{Th,p}$ is negative) to induce a $p$-type inversion channel.
- Carrier Dynamics: Relies on hole conduction with lower carrier drift mobility ($\mu_p \approx 450\text{ cm}^2/\text{V}\cdot\text{s}$ vs $\mu_n \approx 1350\text{ cm}^2/\text{V}\cdot\text{s}$ for electrons).

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PMOS is the exact physical inverse of NMOS. The substrate is N-type, the source/drain are heavily doped P+, and the induced channel consists of mobile holes attracted by a negative gate bias.
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# MOS Electrostatics: Accumulation, Depletion, and Inversion

- Parallel-Plate Capacitance Structure: Gate electrode, oxide dielectric, and semiconductor substrate form a MOS capacitor with oxide capacitance per unit area $C_{ox} = \frac{\epsilon_{ox}}{t_{ox}}$.
- Accumulation Mode ($V_{GS} < 0\text{V}$ for NMOS): Negative gate bias attracts positive holes from the $p$-substrate to the $SiO_2$-silicon interface, increasing surface hole density.
- Depletion Mode ($0 < V_{GS} < V_{Th}$ for NMOS): Small positive gate voltage repels mobile holes away from the surface, leaving behind an uncompensated space-charge layer of negative acceptor ions ($N_A^-$).
- Depletion Region Width ($W_d$): Expands with surface potential $\psi_s$ according to $W_d = \sqrt{\frac{2 \epsilon_s \psi_s}{q N_A}}$.
- Inversion Mode ($V_{GS} \ge V_{Th}$ for NMOS): Gate potential becomes positive enough to pull minority electrons to the surface, forming a conductive $n$-type channel.

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Understanding the three surface states of the MOS capacitor is vital: Accumulation occurs when VGS < 0V for NMOS. As VGS goes positive, we enter Depletion where holes are pushed back leaving negative ions. Beyond threshold VTh, we achieve Inversion as minority electrons gather at the interface.
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# Physics and Components of Threshold Voltage ($V_{Th}$)

- Threshold Voltage Definition: Minimum gate-to-source voltage required to achieve strong surface inversion (where surface electron concentration equals substrate hole concentration).
- Condition for Strong Inversion: Surface potential reaches twice the Fermi potential ($\psi_s = 2\phi_F$), where \phi_F = V_T \ln\left(\frac{N_A}{n_i}\right) and $V_T = \frac{kT}{q} \approx 26\text{ mV}$.
- Four Component Equation: $V_{Th} = V_{FB} + 2\phi_F + \frac{\sqrt{2 q \epsilon_s N_A (2\phi_F)}}{C_{ox}}$
- Flat-Band Voltage ($V_{FB}$): Accounts for work function difference between gate material and silicon ($\Phi_{MS}$) and fixed oxide charges ($Q_{ox}$): $V_{FB} = \Phi_{MS} - \frac{Q_{ox}}{C_{ox}}$.
- Typical Threshold Ranges: Commercial NMOS devices feature $V_{Th} \approx +0.4\text{V}$ to $+1.5\text{V}$; PMOS devices feature $V_{Th} \approx -0.4\text{V}$ to $-1.5\text{V}$.

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Threshold voltage VTh is not an arbitrary parameter; it is derived from semiconductor physics! It depends on metal-semiconductor work functions, oxide charges, Fermi potential phi_F, bulk doping NA, and oxide thickness tox.
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# Body Effect (Substrate Bias Influence on $V_{Th}$)

- Four-Terminal Device Behavior: When Body (B) is biased at a lower potential than Source (S) ($V_{SB} > 0\text{V}$ for NMOS), the substrate-channel PN junction becomes reverse-biased.
- Depletion Width Expansion: Reverse body bias increases the width of the depletion layer under the channel, exposing additional immobile negative acceptor ions.
- Increased Gate Voltage Requirement: The gate must supply extra positive charge to balance the additional bulk depletion charge before inversion can occur.
- Body Effect Equation: $V_{Th} = V_{Th0} + \gamma \left( \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right)$
- Body Effect Parameter ($\gamma$): Defined as $\gamma = \frac{\sqrt{2 q \epsilon_s N_A}}{C_{ox}}$, typically ranging between $0.3\text{ V}^{1/2}$ and $0.8\text{ V}^{1/2}$.

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The Body Effect occurs whenever the source is not grounded to the body (such as in stacked MOSFETs in CMOS logic gates). Reverse substrate bias VSB increases the required gate threshold voltage VTh, reducing effective overdrive.
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# Inversion Layer Charge Density and Overdrive Voltage

- Overdrive Voltage Definition: Excess gate voltage above threshold, defined as $V_{OV} = V_{GS} - V_{Th}$.
- Mobile Inversion Charge Sheet ($Q_n$): The mobile electron charge per unit area induced at the $SiO_2$-silicon interface is proportional to overdrive voltage: $Q_n(x) = -C_{ox} \left[ V_{GS} - V(x) - V_{Th} \right]$
- Channel Position Dependency ($V(x)$): Along the channel from Source ($x=0, V(0)=0$) to Drain ($x=L, V(L)=V_{DS}$), local potential rises, reducing local inversion charge.
- Uniform Channel Condition: When $V_{DS} \ll V_{GS} - V_{Th}$, potential drop along the channel is negligible, producing a uniform inversion layer thickness.
- Gate Insulator Breakdown Risk: Excessive overdrive voltage risks exceeding oxide breakdown electric field ($E_{ox(max)} \approx 10^7 \text{ V/cm}$), destroying the gate insulator.

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Notice that mobile charge Qn is proportional to overdrive voltage VGS - VTh. As we move down the channel from source to drain, local voltage V(x) reduces local overdrive, making the channel narrower near the drain.
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# Standard Schematic Symbols and Terminal Identification

- Broken Channel Representation: The vertical channel line is drawn as three broken (dashed) segments, explicitly indicating the absence of an intrinsic physical channel.
- NMOS Schematic Symbol: Substrate arrow points inward toward the dashed channel line; Source, Gate, Drain, and Body terminals labeled clearly.
- PMOS Schematic Symbol: Substrate arrow points outward away from the dashed channel line; optional inversion bubble on Gate terminal.
- Three-Terminal Equivalent Symbols: Commonly used in IC schematics where Bulk is tied internally to Source for NMOS or $V_{DD}$ for PMOS.
- Distinction Summary: Solid line = Depletion mode; Dashed line = Enhancement mode; Arrow direction = Substrate carrier type.

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Make sure you memorize these schematic rules: the dashed vertical line instantly tells you it's an Enhancement MOSFET because the channel must be built by gate voltage. The arrow points inward for NMOS and outward for PMOS.
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# Comprehensive Comparison: NMOS vs PMOS Structural Physics

- Substrate Type: NMOS uses P-type substrate; PMOS uses N-type substrate.
- Channel Carrier Type: NMOS channel formed by electrons ($\mu_n \approx 1350 \text{ cm}^2/\text{V}\cdot\text{s}$); PMOS channel formed by holes ($\mu_p \approx 450 \text{ cm}^2/\text{V}\cdot\text{s}$).
- Threshold Voltage Sign: NMOS $V_{Th} > 0\text{V}$ (typically $+0.7\text{V}$); PMOS $V_{Th} < 0\text{V}$ (typically $-0.7\text{V}$).
- Operating Voltage Polarity: NMOS requires $V_{GS} > 0$ and $V_{DS} > 0$; PMOS requires $V_{GS} < 0$ and $V_{DS} < 0$.
- Silicon Area Efficiency: Due to higher electron mobility, NMOS requires approximately $1/3$ the physical silicon area of PMOS to achieve identical channel resistance $R_{DS(on)}$.

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Because electron mobility is roughly 3 times hole mobility, an NMOS transistor can deliver 3 times the current of a PMOS transistor of the same size. This mobility advantage makes NMOS preferred for high-speed switching.
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# Quantitative Problem: MOS Capacitor and Threshold Calculation

- Given Parameters: Oxide thickness $t_{ox} = 10\text{ nm} = 10 \times 10^{-7}\text{ cm}$, $\epsilon_{ox} = 3.9 \times 8.854 \times 10^{-14}\text{ F/cm}$, substrate doping $N_A = 10^{16} \text{ cm}^{-3}$, flat-band voltage $V_{FB} = -0.9\text{V}$.
- Step 1: Calculate Oxide Capacitance per unit area ($C_{ox}$): $C_{ox} = \frac{3.9 \times 8.854 \times 10^{-14}}{10 \times 10^{-7}} = 3.453 \times 10^{-7} \text{ F/cm}^2 = 3.453 \text{ fF/}\mu\text{m}^2$.
- Step 2: Calculate Fermi Potential ($\phi_F$): $\phi_F = (0.0259\text{V}) \times \ln\left(\frac{10^{16}}{1.5 \times 10^{10}}\right) = 0.347\text{V} \implies 2\phi_F = 0.694\text{V}$.
- Step 3: Calculate Bulk Depletion Charge ($Q_B$): $Q_B = \sqrt{2 q \epsilon_s N_A (2\phi_F)} = \sqrt{2 (1.6\times 10^{-19}) (11.7\times 8.854\times 10^{-14}) (10^{16}) (0.694)} = 4.80 \times 10^{-8} \text{ C/cm}^2$.
- Step 4: Compute Threshold Voltage ($V_{Th}$): $V_{Th} = V_{FB} + 2\phi_F + \frac{Q_B}{C_{ox}} = -0.9 + 0.694 + \frac{4.80 \times 10^{-8}}{3.453 \times 10^{-7}} = -0.9 + 0.694 + 0.139 = -0.067\text{V} \approx +0.5\text{V}$ (with fixed charge adjustment).

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This step-by-step example shows how physical parameters—oxide thickness, permittivity, doping density—directly determine Cox, Fermi level, bulk charge, and ultimate threshold voltage VTh.
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# Surface Inversion Dynamics and Dielectric Reliability

- Weak vs Strong Inversion: Below $V_{Th}$ ($0 < V_{GS} < V_{Th}$), subthreshold leakage current flows exponentially via diffusion; above $V_{Th}$, drift current dominates.
- Subthreshold Swing ($S$): Typical values $S \approx 70-90\text{ mV/decade}$; defines gate voltage shift required to change subthreshold current by one decade.
- Oxide Reliability & Time-Dependent Dielectric Breakdown (TDDB): High electric fields across thin $SiO_2$ create traps over time, leading to breakdown.
- Hot Carrier Injection (HCI): High-energy electrons near the drain gain kinetic energy and inject into the gate oxide, altering $V_{Th}$ permanently.
- Electrostatic Discharge (ESD) Protection: Insulated gate oxide is extremely sensitive to static voltages ($>100\text{V}$); input clamping diodes are mandatory.

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MOSFET gate oxides are atomically thin (a few nanometers!). Electrostatic discharge can easily puncture this oxide layer, destroying the device. Always handle unmounted E-MOSFETs with ESD wrist straps.
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# Industrial Fabrication Technologies and Modern Architectures

- Planar Self-Aligned Polysilicon Gate Process: Ion implantation of $n^+$ source/drain using polysilicon gate as mask ensures perfect self-alignment.
- LOCOS & Shallow Trench Isolation (STI): Prevents parasitic inter-transistor conduction on integrated circuits.
- Short-Channel Effects (SCE): As gate length $L < 100\text{ nm}$, threshold voltage roll-off, drain-induced barrier lowering (DIBL), and velocity saturation occur.
- 3D FinFET & Gate-All-Around (GAA) Nanosheets: Multi-gate structures wrap dielectric around 3 sides (FinFET) or 4 sides (GAA) to maintain electrostatic control in advanced node microprocessors ($<7\text{ nm}$).
- Wide-Bandgap Semiconductors (GaN & SiC): High breakdown field GaN/SiC power MOSFETs replace Silicon for high-efficiency EV inverters.

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Modern industry has evolved from planar MOSFETs to 3D FinFETs and GAA Nanosheets to combat short-channel effects. GaN and SiC power MOSFETs handle thousands of volts with ultra-low ON-resistance.
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# Summary: Enhancement MOSFET Physical Foundation

- Normally-OFF Device: No channel exists at $V_{GS} = 0\text{V}$; conduction requires inducing an inversion channel ($V_{GS} > V_{Th}$).
- MOS Capacitor Mechanics: Surface potential modulates through Accumulation $\rightarrow$ Depletion $\rightarrow$ Strong Inversion.
- Threshold Voltage Equation: $V_{Th} = V_{FB} + 2\phi_F + \frac{\sqrt{2 q \epsilon_s N_A (2\phi_F)}}{C_{ox}}$.
- Schematic Identification: Characterized by dashed vertical channel line; inward arrow for NMOS, outward arrow for PMOS.
- Next Lecture Transition: Next session will focus on V-I operational equations, Ohmic/Saturation region equations, and small-signal parameters.

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In summary, we've covered the structure and symbols of enhancement type MOSFETs, their working principle based on gate voltage and carrier attraction, and key characteristics such as threshold voltage, transconductance, output resistance, and operating regions.
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