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title: 'Lecture 5: Depletion type MOSFET'
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  ## DI02011011: Electronics Circuit and Application (ECA)
  Field Effect Transistors(FETs)
---

# DI02011011: Electronics Circuit and Application (ECA)
## Lecture 5: Depletion type MOSFET
### Field Effect Transistors(FETs)

<!--
Welcome to Lecture 5! Today we focus on the Depletion-Type MOSFET, commonly referred to as D-MOSFET. Unlike E-MOSFETs which are normally-OFF, D-MOSFETs contain a physically built-in channel during fabrication. This unique feature allows them to operate seamlessly in two distinct modes: depletion mode (like a JFET) and enhancement mode (like an E-MOSFET).
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# Lecture Outline: D-MOSFET Physical Construction, Dual-Mode Dynamics, and Parameters

- Physical Architecture: Substrate foundation, $n^+$ wells, pre-formed physical channel, and dielectric $SiO_2$ layer.
- Schematic Symbols: Continuous channel line vs isolated gate representation for N-channel and P-channel D-MOSFETs.
- Zero-Bias Conduction ($V_{GS}=0\text{V}$): Maximum uncontrolled channel current $I_{DSS}$ and non-pinched channel conduction.
- Depletion-Mode Operation ($V_{GS} < 0\text{V}$ for N-Channel): Electrostatic electron repulsion, channel constriction, and pinch-off voltage $V_P$.
- Enhancement-Mode Operation ($V_{GS} > 0\text{V}$ for N-Channel): Carrier accumulation, channel conductivity enhancement, and $I_D > I_{DSS}$.
- Mathematical Formulation: Application of Shockley's square-law equation across negative and positive gate bias zones.
- Drain ($I_D$ vs $V_{DS}$) & Transfer ($I_D$ vs $V_{GS}$) Curves: Graphical boundaries, Ohmic region, saturation, and breakdown.
- Comparative Parameter Analysis: Input impedance $R_{in} \ge 10^{14}\,\Omega$, $g_m$ derivation, and practical circuit applications.

<!--
Here is our lecture outline. We will systematically cover physical structure, schematic representations, zero-bias state, depletion mode, enhancement mode, unified mathematical modeling, graphical I-V curves, and practical circuit applications.
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# Physical Construction and Internal Anatomy of N-Channel D-MOSFET

- Substrate Foundation: Formed on a lightly-doped P-type silicon substrate ($p$-substrate) providing structural support and electrical isolation.
- Source & Drain Diffusion Wells: Heavily-doped $n^+$ regions ($N_D \approx 10^{19} \text{ cm}^{-3}$) diffused into the substrate forming low-resistance ohmic contacts.
- Pre-formed Physical Channel: A narrow N-type channel is physically diffused between the $n^+$ Source and Drain wells prior to gate oxide deposition.
- Insulating Gate Dielectric: A thin layer of Silicon Dioxide ($SiO_2$, thickness $t_{ox} \approx 10\text{ nm} - 50\text{ nm}$) grown directly over the channel region.
- Gate Electrode: Polysilicon or metallic aluminum deposited on top of the $SiO_2$ layer, forming a parallel-plate metal-insulator-semiconductor capacitor.
- Substrate (Body) Terminal: Connected internally to Source ($V_{BS} = 0\text{V}$) or brought out as a fourth terminal.

<!--
Examine the physical structure of the N-channel D-MOSFET. Notice the key difference compared to an E-MOSFET: there is a physically built-in N-channel connecting the source and drain wells beneath the oxide layer. Because this channel exists naturally, current flows freely even when VGS = 0V.
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# Schematic Symbols and Terminal Identification for D-MOSFETs

- Continuous Channel Line: Represented by a solid vertical line connecting Drain (D) and Source (S), symbolizing a physically built-in channel (unlike the broken line in E-MOSFETs).
- Insulated Gate Gap: The Gate (G) terminal is drawn separated from the channel line by a distinct dielectric gap, representing the non-conductive $SiO_2$ insulating barrier.
- Substrate/Body Arrow (N-Channel): Arrow on the Bulk (B) terminal points inward toward the N-channel, indicating the P-substrate to N-channel PN junction polarity.
- Substrate/Body Arrow (P-Channel): Arrow on the Bulk (B) terminal points outward from the P-channel toward the N-substrate.
- Three-Terminal vs Four-Terminal Conventions: Simplified 3-terminal symbols show the internal substrate-to-source connection, eliminating the separate Bulk pin.

<!--
Pay close attention to schematic symbols. The solid unbroken vertical line between drain and source immediately identifies a Depletion-Type MOSFET (indicating a continuous built-in channel). In contrast, Enhancement-Type MOSFETs use a broken dashed line.
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# Zero-Bias Equilibrium Operation ($V_{GS} = 0\text{V}$)

- Unbiased Channel State: With $V_{GS} = 0\text{V}$, the physical N-channel retains its initial fabrication width and free electron concentration.
- Drain Current Conduction: Applying $V_{DS} > 0\text{V}$ causes free electrons to drift from Source to Drain through the built-in channel.
- Definition of $I_{DSS}$: The saturated drain current flowing through the device at $V_{GS} = 0\text{V}$ is designated as $I_{DSS}$ (Drain-to-Source Current at Shorted Gate).
- Comparison with JFET and E-MOSFET:
- • JFET: $I_D = I_{DSS}$ at $V_{GS} = 0\text{V}$ (Gate cannot be forward-biased $> +0.7\text{V}$).
- • E-MOSFET: $I_D = 0\text{ A}$ at $V_{GS} = 0\text{V}$ (Requires $V_{GS} > V_{th}$ to conduct).
- • D-MOSFET: $I_D = I_{DSS}$ at $V_{GS} = 0\text{V}$ (Gate can be biased both negatively AND positively!).

<!--
At zero gate voltage, the D-MOSFET conducts current IDSS just like a JFET. But here is the major advantage of the D-MOSFET over the JFET: because the gate is insulated by oxide rather than a PN junction, we are not restricted to negative gate voltages! We can apply positive gate voltages as well.
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# Depletion-Mode Operation ($V_{GS} < 0\text{V}$ for N-Channel)

- Electrostatic Repulsion Mechanics: Applying negative voltage to the Gate ($V_{GS} < 0\text{V}$) deposits negative charge on the gate electrode.
- Depletion Layer Formation: Negative gate charge repels free electrons out of the N-channel into the substrate, uncovering positive donor ions ($N_D^+$).
- Channel Constriction: Repulsion of free electrons widens the depletion region into the channel, reducing effective cross-sectional conducting area.
- Current Reduction: Channel resistance increases, causing drain current $I_D$ to drop below $I_{DSS}$ ($I_D < I_{DSS}$).
- Pinch-Off Cutoff Voltage ($V_P$): As $V_{GS}$ becomes increasingly negative, reaching $V_{GS} = V_P$ (e.g., $-4\text{V}$), the channel is completely depleted of free electrons, cutting off drain current ($I_D = 0\text{ A}$).

<!--
When we apply negative VGS to an N-channel D-MOSFET, we operate in Depletion Mode. Negative charge on the gate repels electrons out of the channel, widening the depletion region and constricting current flow. When VGS reaches pinch-off voltage Vp, the channel is completely depleted and ID drops to zero.
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# Enhancement-Mode Operation ($V_{GS} > 0\text{V}$ for N-Channel)

- Electrostatic Accumulation Mechanics: Applying positive voltage to the Gate ($V_{GS} > 0\text{V}$) deposits positive charge on the gate electrode.
- Carrier Attraction: Positive gate charge attracts additional free electrons from the P-substrate into the physical N-channel.
- Channel Conductivity Enhancement: The concentration of mobile electrons in the channel rises above the initial donor doping concentration ($n > N_D$).
- Current Expansion: Effective channel resistance decreases, causing drain current $I_D$ to increase significantly above $I_{DSS}$ ($I_D > I_{DSS}$).
- No Gate Breakdown Risk: Oxide insulator $SiO_2$ prevents gate current from flowing ($I_G = 0\text{ A}$), even under large positive gate bias (up to oxide breakdown limits).

<!--
Now observe what happens when we apply positive VGS to an N-channel D-MOSFET: we operate in Enhancement Mode! Positive gate bias attracts extra electrons into the built-in channel, increasing its conductivity. The drain current ID increases above IDSS. Because of the SiO2 layer, no gate current flows!
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# Unified Shockley Equation Modeling Across Dual Modes

- Mathematical Equation: In the saturation region ($V_{DS} \ge V_{GS} - V_P$), drain current across BOTH depletion and enhancement modes is governed by Shockley's Square Law:
- $$I_D = I_{DSS} \left( 1 - \frac{V_{GS}}{V_P} \right)^2$$
- Depletion Region Bounds ($V_P \le V_{GS} \le 0\text{V}$): Term $\left(1 - \frac{V_{GS}}{V_P}\right) < 1$, resulting in $I_D < I_{DSS}$.
- Enhancement Region Bounds ($V_{GS} > 0\text{V}$): Term $\left(1 - \frac{V_{GS}}{V_P}\right) > 1$ (since $V_P$ is negative), resulting in $I_D > I_{DSS}$.
- Transconductance Expression: $g_m = \frac{\partial I_D}{\partial V_{GS}} = \frac{2 I_{DSS}}{|V_P|} \left( 1 - \frac{V_{GS}}{V_P} \right) = g_{m0} \left( 1 - \frac{V_{GS}}{V_P} \right)$.
- Transconductance Enhancement: In enhancement mode ($V_{GS} > 0$), transconductance $g_m$ exceeds zero-bias transconductance $g_{m0}$ ($g_m > g_{m0}$).

<!--
Shockley's equation applies seamlessly across both depletion and enhancement operating modes for D-MOSFETs! When VGS is positive, the ratio VGS/Vp becomes positive (since Vp is negative), making (1 - VGS/Vp) greater than 1, so ID exceeds IDSS and gm exceeds gm0.
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# Complete Output Drain Characteristics ($I_D$ vs $V_{DS}$)

- Ohmic / Linear Region ($V_{DS} < V_{GS} - V_P$): Linear slope where channel acts as voltage-controlled resistor; slope increases with positive $V_{GS}$.
- Pinch-Off Saturation Boundary ($V_{DS,sat} = V_{GS} - V_P$): Parabolic boundary separating linear region from saturated constant-current region.
- Saturation Region ($V_{DS} \ge V_{GS} - V_P$): Curves flatten into constant current plateaus corresponding to $I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2$.
- Family of Curves Profile:
- • Top Curves ($V_{GS} > 0\text{V}$): Enhancement mode operation ($I_D > I_{DSS}$).
- • Middle Curve ($V_{GS} = 0\text{V}$): Baseline zero-bias curve ($I_D = I_{DSS}$).
- • Bottom Curves ($V_P < V_{GS} < 0\text{V}$): Depletion mode operation ($I_D < I_{DSS}$).
- • Axis Cutoff ($V_{GS} = V_P$): Flat horizontal line along x-axis ($I_D = 0\text{ A}$).

<!--
Examine the output characteristic family of curves. At VGS = 0, current saturates at IDSS. When VGS goes positive (enhancement mode), the curves shift upward to higher current plateaus. When VGS goes negative (depletion mode), the curves shift downward until VGS = Vp where current is zero.
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# Complete Transfer Characteristic ($I_D$ vs $V_{GS}$)

- Continuous Parabolic Curve: A unbroken parabolic arc extending continuously across the $y$-axis ($V_{GS} = 0\text{V}$).
- Left-Hand Side ($V_P \le V_{GS} \le 0\text{V}$): Depletion region where $I_D$ decreases quadratically from $I_{DSS}$ down to zero at $V_{GS} = V_P$.
- Right-Hand Side ($V_{GS} > 0\text{V}$): Enhancement region where $I_D$ increases quadratically above $I_{DSS}$ without upper theoretical bound (limited by thermal power dissipation).
- Point of Inflection ($y$-intercept): At $V_{GS} = 0\text{V}$, $I_D = I_{DSS}$ and curve slope equals $g_{m0} = \frac{2 I_{DSS}}{|V_P|}$.
- Comparison with E-MOSFET: E-MOSFET transfer curve exists strictly for $V_{GS} > V_{th} > 0$, whereas D-MOSFET transfer curve spans negative and positive gate voltages.

<!--
The transfer characteristic curve of a D-MOSFET is uniquely continuous across the vertical axis. To the left of VGS=0, it operates in depletion mode. To the right of VGS=0, it operates smoothly in enhancement mode. This continuous curve is modeled by Shockley's equation across its entire span.
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# Complementary Construction: P-Channel Depletion MOSFET

- Structural Reversal: Built on an N-type silicon substrate ($n$-sub) with heavily-doped $p^+$ Source and Drain diffusion wells.
- Built-in P-Channel: A physical P-type channel connects the $p^+$ Source and Drain regions beneath the $SiO_2$ oxide layer.
- Polarity Conventions: Conducts majority hole current under negative drain bias ($V_{DS} < 0\text{V}$). Pinch-off voltage $V_P$ is POSITIVE ($V_P > 0\text{V}$).
- P-Channel Operating Regimes:
- • Depletion Mode ($V_{GS} > 0\text{V}$): Positive gate voltage repels holes, reducing channel width and $I_D < I_{DSS}$.
- • Enhancement Mode ($V_{GS} < 0\text{V}$): Negative gate voltage attracts additional holes, increasing $I_D > I_{DSS}$.
- • Cutoff State ($V_{GS} \ge V_P > 0\text{V}$): Channel completely depleted ($I_D = 0\text{ A}$).

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P-channel D-MOSFETs reverse all voltage polarities. The built-in channel is P-type, and Vp is positive. Positive VGS operates in depletion mode, while negative VGS operates in enhancement mode.
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# Parameter Comparison: JFET vs D-MOSFET vs E-MOSFET

- 1. Built-in Channel Presence:
- • JFET: Yes (Physical channel exists).
- • D-MOSFET: Yes (Physical channel exists).
- • E-MOSFET: No (Induced channel only).
- 2. Gate Isolation Dielectric:
- • JFET: Reverse-biased PN junction ($R_{in} \approx 10^8 - 10^{11} \,\Omega$).
- • D-MOSFET & E-MOSFET: $SiO_2$ oxide insulator ($R_{in} \approx 10^{14} - 10^{15} \,\Omega$).
- 3. Allowed Gate Bias Polarities (N-Channel):
- • JFET: Negative only ($V_P \le V_{GS} \le 0\text{V}$).
- • D-MOSFET: Negative AND Positive ($V_P \le V_{GS} < +\infty$).
- • E-MOSFET: Positive only ($V_{GS} \ge V_{th} > 0\text{V}$).
- 4. Mathematical Governing Equations:
- • JFET & D-MOSFET: Shockley Square Law ($I_D = I_{DSS}(1 - V_{GS}/V_P)^2$).
- • E-MOSFET: E-MOSFET Square Law ($I_D = \frac{1}{2} k_n' \frac{W}{L} (V_{GS} - V_{th})^2$).

<!--
This comparative table consolidates the entire FET family! Understand the structural reasons behind each difference: presence of built-in channel dictates zero-bias conduction; oxide insulation dictates input resistance and allowed gate polarities.
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# Quantitative Numerical Example: D-MOSFET Dual-Mode Computations

- Problem Statement: An N-channel D-MOSFET has datasheet parameters $I_{DSS} = 10\text{ mA}$ and $V_P = -4.0\text{V}$. Compute the drain current $I_D$ and transconductance $g_m$ for:
- (a) $V_{GS} = -2.0\text{V}$ (Depletion Mode)
- (b) $V_{GS} = 0\text{V}$ (Zero-Bias State)
- (c) $V_{GS} = +1.5\text{V}$ (Enhancement Mode)
- 1. Calculate Zero-Bias Transconductance $g_{m0}$:
- $$g_{m0} = \frac{2 I_{DSS}}{|V_P|} = \frac{2(10\text{ mA})}{4.0\text{V}} = 5.0\text{ mS}$$
- 2. Case (a) $V_{GS} = -2.0\text{V}$ (Depletion Mode):
- $$I_D = 10\text{ mA} \left(1 - \frac{-2.0}{-4.0}\right)^2 = 10 (0.5)^2 = 2.50\text{ mA}, \quad g_m = 5.0\text{ mS}(1 - 0.5) = 2.50\text{ mS}$$
- 3. Case (b) $V_{GS} = 0\text{V}$ (Zero-Bias State):
- $$I_D = 10\text{ mA} \left(1 - 0\right)^2 = 10.0\text{ mA}, \quad g_m = g_{m0} = 5.00\text{ mS}$$
- 4. Case (c) $V_{GS} = +1.5\text{V}$ (Enhancement Mode):
- $$I_D = 10\text{ mA} \left(1 - \frac{1.5}{-4.0}\right)^2 = 10 \left(1 + 0.375\right)^2 = 10(1.375)^2 = 18.91\text{ mA}$$
- $$g_m = 5.0\text{ mS} \left(1 - \frac{1.5}{-4.0}\right) = 5.0 (1.375) = 6.875\text{ mS}$$

<!--
Walk through this quantitative example carefully. Notice how operating in depletion mode at VGS = -2V cuts current down to 2.5 mA, while operating in enhancement mode at VGS = +1.5V boosts current up to 18.91 mA and increases transconductance gm to 6.875 mS!
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# Comprehensive Summary: D-MOSFET Dual-Mode Principles & Circuit Roles

- Physical Structure: Built-in physical channel insulated by $SiO_2$ dielectric, providing ultra-high input impedance ($R_{in} \ge 10^{14}\,\Omega$).
- Dual-Mode Operating Flexibility:
- 1. Depletion Mode ($V_{GS} < 0\text{V}$ for N-channel): Negative gate bias repels majority carriers, constricting channel ($I_D < I_{DSS}$).
- 2. Enhancement Mode ($V_{GS} > 0\text{V}$ for N-channel): Positive gate bias attracts additional carriers, enhancing channel ($I_D > I_{DSS}$).
- 3. Cutoff State ($V_{GS} \le V_P$): Total channel depletion ($I_D = 0\text{ A}$).
- Unified Mathematical Model: Shockley's relation $I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2$ governs both operating modes in saturation.
- Applications: Constant current sources, high-input-impedance AC amplifiers, and zero-bias self-biased stages.

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To wrap up Lecture 5: D-MOSFETs offer unmatched biasing versatility because of their built-in physical channel and insulated gate structure, allowing continuous dual-mode operation across depletion and enhancement regimes.
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