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title: 'Lecture 1: Junction field effect transistor(JFET) structure, symbol, working, characteristics, parameters'
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  ## DI02011011: Electronics Circuit and Application (ECA)
  Field Effect Transistors(FETs)
---

# DI02011011: Electronics Circuit and Application (ECA)
## Lecture 1: Junction field effect transistor(JFET) structure, symbol, working, characteristics, parameters
### Field Effect Transistors(FETs)

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Welcome everyone! Today we begin our deep dive into Field Effect Transistors (FETs) by examining the Junction Field Effect Transistor (JFET). Unlike Bipolar Junction Transistors which are current-controlled bipolar devices, JFETs are unipolar, voltage-controlled devices. We will systematically examine their construction, electrostatic channel modulation, pinch-off physics, and mathematical current equations.
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# Lecture Outline: JFET Fundamentals, Device Physics, and Analytical Modeling

- Transistor Classification: Comparison between Bipolar Junction Transistors (BJT) and Unipolar Field Effect Transistors (FET).
- Physical Construction & Materials: N-channel and P-channel semiconductor geometries, ohmic contacts, and heavily doped $p^+$ gate wells.
- Schematic Representation: Circuit symbols, terminal polarities ($D, S, G$), and conventional current flow vectors.
- Zero-Bias Equilibrium ($V_{GS}=0\text{V}, V_{DS}=0\text{V}$): Built-in potential, depletion boundary profile, and equilibrium channel width.
- Ohmic Operating Region ($V_{DS} < |V_P|$): Linear channel resistance $r_{ds0}$, majority carrier drift, and current dependence on $V_{DS}$.
- Pinch-Off Mechanics & Saturation ($V_{DS} \ge V_{DS,sat}$): Asymmetric depletion widening, channel constriction, and velocity saturation.
- Gate Voltage Control ($V_{GS} < 0\text{V}$): Electrostatic channel narrowing, modified pinch-off boundaries, and Shockley's parabolic model.

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This outline structures our examination of JFETs. We will transition from basic physical architecture to electrostatic field behavior, leading directly into the quantitative derivation of the drain current equation and graphical characterization.
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# Classification of Transistors & Principles of Voltage Control

- Unipolar vs Bipolar Conduction: BJTs rely on dual carrier injection (electrons and holes), whereas JFET conduction relies strictly on majority carriers (electrons in N-channel, holes in P-channel).
- Control Mechanism: BJT collector current is controlled by base current ($I_C = \beta I_B$), while JFET drain current is modulated by reverse gate voltage $V_{GS}$ ($I_G \approx 0\text{ A}$).
- Input Impedance Superiority: Reverse-biased gate-channel PN junction provides ultra-high input impedance ($R_{in} \approx 10^8 \text{ to } 10^{11} \,\Omega$), minimizing loading on signal sources.
- Thermal Stability & Noise Performance: Absence of minority carrier storage effects eliminates thermal runaway risks and yields significantly lower flicker/shot noise compared to BJTs.

<!--
It is critical to contrast FETs with BJTs. In a BJT, base current flows, creating power dissipation at the input stage. In contrast, the JFET gate is reverse-biased, presenting an extremely high input resistance. This makes JFETs ideal for high-impedance buffer stages and sensitive preamplifiers.
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# Physical Construction and Internal Geometry of N-Channel JFET

- Substrate Body & Channel Bar: Consists of a lightly-doped N-type silicon bar ($N_D \approx 10^{15} \text{ cm}^{-3}$) providing a conductive path between Source and Drain terminals.
- Heavily Doped Gate Regions: Two high-concentration $p^+$ regions ($N_A \approx 10^{18} \text{ cm}^{-3}$) diffused on opposite sides of the N-channel bar.
- Internal Gate Connection: The two $p^+$ regions are electrically connected internally or externally to form a single Gate terminal ($G$).
- Ohmic Contact Terminals: Metallic contacts at both ends of the N-bar form the Source ($S$) terminal (carrier entry) and Drain ($D$) terminal (carrier collection).
- Depletion Region Penetration: Due to asymmetrical doping ($N_A \gg N_D$), the PN junction depletion regions extend almost entirely into the lightly-doped N-channel.

<!--
Notice the geometry of the N-channel JFET. The N-bar is lightly doped, while the p+ gate inserts are heavily doped. When a PN junction is formed between heavily doped p+ and lightly doped n-silicon, the space-charge depletion region extends predominantly into the lightly doped n-channel. This asymmetric penetration is key to controlling channel width.
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# Physical Construction & Carrier Mobility of P-Channel JFET

- Complementary Layout: Built using a lightly-doped P-type silicon bar ($N_A \approx 10^{15} \text{ cm}^{-3}$) flanked by two heavily-doped $n^+$ gate diffusion regions ($N_D \approx 10^{18} \text{ cm}^{-3}$).
- Majority Carrier Dynamics: Conduction occurs via hole transport through the P-channel under an applied negative drain-to-source bias ($V_{DS} < 0\text{V}$).
- Mobility Comparison: Hole drift mobility in silicon ($\mu_p \approx 450 \text{ cm}^2/\text{V}\cdot\text{s}$) is roughly one-third of electron mobility ($\mu_n \approx 1350 \text{ cm}^2/\text{V}\cdot\text{s}$).
- Performance Implication: For identical physical dimensions, P-channel JFETs exhibit higher channel resistance $R_{DS(on)}$ and lower transconductance $g_m$ compared to N-channel counterparts.

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P-channel JFETs operate on identical electrostatic field principles but with opposite voltage polarities and charge carriers. Hole mobility is significantly lower than electron mobility, which means P-channel devices require larger silicon area to achieve equivalent ON-resistance.
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# Schematic Symbols, Terminal Conventions, and Voltage Polarities

- N-Channel Symbol: Features an arrow on the Gate terminal pointing inward toward the channel bar (representing $p^+ \to n$ junction polarity).
- P-Channel Symbol: Features an arrow on the Gate terminal pointing outward away from the channel bar ($p \to n^+$ polarity).
- Terminal Voltage Definitions: For N-channel, Drain is biased positive relative to Source ($V_{DS} > 0\text{V}$); Gate is biased negative relative to Source ($V_{GS} \le 0\text{V}$).
- Gate Current Nullity Constraint: Under normal operating conditions, the Gate-Channel PN junction remains strictly reverse-biased, keeping gate current $I_G = 0\text{ A}$ (practically $I_{GSS} < 1\text{ nA}$).
- Channel Continuity Equation: Kirchoff's Current Law yields $I_S = I_D + I_G \approx I_D$ under all standard bias states.

<!--
Always remember the symbol conventions! The arrow direction on the gate points in the direction of forward PN junction current (from p to n). For N-channel, it points IN. For P-channel, it points OUT. Since we keep the gate reverse-biased, no gate current flows, making drain current equal to source current.
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# Zero-Bias Thermal Equilibrium State ($V_{GS} = 0\text{V}, V_{DS} = 0\text{V}$)

- Built-in Potential Bar: With no external voltages applied, a uniform depletion layer forms at the $p^+ n$ junctions with built-in potential $V_{bi} = \frac{kT}{q} \ln\left(\frac{N_A N_D}{n_i^2}\right) \approx 0.7\text{V}$.
- Equilibrium Depletion Width: Space-charge depletion thickness $W_0 = \sqrt{\frac{2\varepsilon_s V_{bi}}{q N_D}}$ penetrates symmetrically into both sides of the N-channel.
- Unconstricted Conducting Path: A wide, uniform conductive channel exists between Source and Drain, offering maximum initial channel cross-sectional area.
- Zero Net Drift Current: In thermal equilibrium, electron diffusion current is exactly balanced by drift current across the junction barriers, resulting in $I_D = 0\text{ A}$.

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At zero bias, the JFET already has a physical channel open. Built-in potential creates small depletion regions near the gate contacts, but the central channel remains open and conductive. This makes the JFET a depletion-mode (normally-ON) device.
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# Low Drain-Source Bias Operation ($V_{DS} > 0\text{V}, V_{GS} = 0\text{V}$): Ohmic Region

- Electric Field Setup: Applying a small positive voltage $V_{DS}$ creates an axial electric field $E_x = \frac{V_{DS}}{L}$ along the length of the channel.
- Linear Majority Drift: Free electrons in the N-channel drift from Source to Drain, producing a drain current $I_D$ proportional to $V_{DS}$.
- Channel Resistance Model: The channel behaves as an ideal linear resistor $r_{ds0}$ given by $r_{ds0} = \frac{L}{q \mu_n N_D A_c}$, where $A_c$ is the channel cross-sectional area.
- Slight Asymmetric Depletion: Potential along the channel increases from $0\text{V}$ at the source end to $V_{DS}$ at the drain end, causing slightly greater reverse bias ($V_{DG} = V_{DS}$) near the drain.

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When small Vds is applied, current flows linearly according to Ohm's law. However, because Vds causes the drain end to be at a higher potential than the source end, the reverse bias across the gate-channel junction is higher near the drain than near the source.
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# Asymmetric Depletion Widening and Pinch-Off Mechanism ($V_{DS} = V_P$)

- Voltage-Drop Gradient: Potential at distance $x$ along channel is $V(x)$, making gate-to-channel reverse bias $V_{GC}(x) = V_{GS} - V(x) = -V(x)$ (for $V_{GS}=0$).
- Maximum Depletion at Drain End: Reverse bias is highest at the Drain terminal where $V_{GC} = -V_{DS}$, causing maximum depletion region width at $x = L$.
- Pinch-Off Point Definition: As $V_{DS}$ reaches the Pinch-off Voltage $V_P$ (e.g., $V_{DS} = |V_P| = 4\text{V}$), the depletion regions touch or nearly touch near the drain end.
- Constricted High-Field Region: Channel cross-section narrows to a minimum wedge shape; electron velocity reaches saturation ($v_{sat} \approx 10^7 \text{ cm/s}$), preventing further current increase.

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This slide captures the core physics of pinch-off. As Vds increases, the depletion region widens more at the drain end than at the source end. When Vds equals the magnitude of the pinch-off voltage, the depletion boundaries meet at the drain end. Channel current does not drop to zero; instead, carriers are swept through the high electric field region at maximum saturation velocity.
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# Saturation Operating Region Physics ($V_{DS} \ge V_{DS,sat}$)

- Current Clamping Behavior: For $V_{DS} > V_P$ (with $V_{GS}=0$), the excess voltage $(V_{DS} - V_P)$ drops across the narrow pinch-off space-charge region.
- Drain Current Saturation ($I_{DSS}$): The drain current remains practically constant at its maximum saturated value $I_D = I_{DSS}$ (Drain-to-Source Current at Zero Bias).
- Channel Length Modulation ($\Delta L$): Increasing $V_{DS}$ further shifts the pinch-off point slightly toward the source, effectively shortening the conductive channel length from $L$ to $L - \Delta L$.
- Output Impedance Effect: Channel shortening introduces a slight upward slope in the $I_D$ vs $V_{DS}$ saturation curve, modeling finite output resistance $r_d = \frac{\partial V_{DS}}{\partial I_D}$.

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Once in saturation, any further increase in Vds is dropped across the high-field pinch-off region. The current remains fixed at IDSS. The minor slope seen in real devices is due to channel length modulation, analogous to the Early effect in BJTs.
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# Gate-Source Reverse Bias Modulation ($V_{GS} < 0\text{V}$)

- Initial Channel Narrowing: Applying negative gate voltage ($V_{GS} < 0\text{V}$) widens depletion regions uniformly along the entire channel prior to applying $V_{DS}$.
- Reduced Effective Pinch-Off Voltage: Pinch-off occurs at a lower drain voltage: $V_{DS,sat} = V_{GS} - V_P = V_{GS} + |V_P|$ (since $V_P$ is negative for N-channel).
- Complete Cutoff State ($V_{GS} \le V_P$): When $V_{GS}$ reaches $V_P$, depletion regions meet completely along the full channel length, reducing drain current to zero ($I_D = 0\text{ A}$).
- Effective Channel Width Formula: $W(x) = a - W_{dep}(x)$, where $a$ is physical channel half-width and $W_{dep}(x) \propto \sqrt{V_{bi} - V_{GS} + V(x)}$.

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When we apply a negative Vgs, we pre-deplete the channel. Therefore, less Vds is needed to pinch off the channel, and the resulting saturation drain current is lower. When Vgs reaches Vp, the channel is pinched off completely even with Vds = 0, cutting off all current.
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# Mathematical Derivation of Shockley's Transconductance Relation

- Integration of Mobile Channel Charge: Integrating Ohm's law along the channel $I_D dx = q \mu_n N_D [2a - 2W_{dep}(x)] W_{width} dV$ yields exact current equations.
- Shockley's Parabolic Approximation: In the saturation region ($V_{DS} \ge V_{GS} - V_P$), the analytical integration reduces to Shockley's Square Law:
- $$I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2$$
- Parameter Boundaries: $I_{DSS}$ is maximum drain current at $V_{GS}=0\text{V}$; $V_P$ is pinch-off cutoff voltage (negative for N-channel, positive for P-channel).
- Valid Bias Range: Shockley's relation is valid strictly for $V_P \le V_{GS} \le 0\text{V}$ (for N-channel) in the saturation operating region.

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Shockley's equation is the fundamental transfer relation for JFETs in saturation. It links drain current ID to gate-source voltage VGS using only two device constants: IDSS and Vp. Note the square-law relationship, which is quadratic, similar to MOSFET square-law models.
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# Comprehensive Numerical Example: JFET Operating Regimes and $Q$-Point

- Problem Statement: An N-channel JFET has parameters $I_{DSS} = 12\text{ mA}$ and $V_P = -4.0\text{V}$. Determine the drain current $I_D$ and minimum drain-source saturation voltage $V_{DS,sat}$ for (a) $V_{GS} = 0\text{V}$, (b) $V_{GS} = -1.5\text{V}$, and (c) $V_{GS} = -3.0\text{V}$.
- Case (a) $V_{GS} = 0\text{V}$:
- $$I_D = 12\text{ mA} \left(1 - \frac{0}{-4}\right)^2 = 12.0\text{ mA}, \quad V_{DS,sat} = 0 - (-4) = 4.0\text{V}$$
- Case (b) $V_{GS} = -1.5\text{V}$:
- $$I_D = 12\text{ mA} \left(1 - \frac{-1.5}{-4}\right)^2 = 12\left(0.625\right)^2 = 4.6875\text{ mA}, \quad V_{DS,sat} = -1.5 - (-4) = 2.5\text{V}$$
- Case (c) $V_{GS} = -3.0\text{V}$:
- $$I_D = 12\text{ mA} \left(1 - \frac{-3.0}{-4}\right)^2 = 12\left(0.25\right)^2 = 0.75\text{ mA}, \quad V_{DS,sat} = -3.0 - (-4) = 1.0\text{V}$$

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Let's work through this step-by-step example. Notice how increasing the magnitude of negative gate voltage drastically reduces ID and lowers the minimum Vds required to enter saturation. At VGS = -3V, ID drops from 12 mA down to 0.75 mA.
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# Comprehensive Summary: JFET Physical Operating Zones & Fundamental Equations

- Unipolar Device Physics: JFETs control majority carrier drift current using reverse-biased PN junction depletion fields without drawing gate current.
- Three Distinct Operating Zones:
- 1. Ohmic / Linear Region ($V_{DS} < V_{GS} - V_P$): Device acts as voltage-controlled resistor $r_{ds}$.
- 2. Saturation / Pinch-off Region ($V_{DS} \ge V_{GS} - V_P$): $I_D$ saturates to constant current governed by $I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2$.
- 3. Cutoff Region ($V_{GS} \le V_P$): Depletion regions merge completely across channel; $I_D = 0\text{ A}$.
- Key Design Parameters: Maximum drain current $I_{DSS}$, pinch-off voltage $V_P$, and high input impedance $R_{in} \ge 10^8\,\Omega$.

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To wrap up today's lecture: remember the three operating regions of the JFET and the key mathematical boundary VDS,sat = VGS - Vp. In the next lecture, we will examine small-signal AC parameters, transconductance, temperature instability, and breakdown phenomena.
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